CMU-SAFARI / MIG-7-PHY-DDR3-ControllerLinks
A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
☆11Updated 4 years ago
Alternatives and similar repositories for MIG-7-PHY-DDR3-Controller
Users that are interested in MIG-7-PHY-DDR3-Controller are comparing it to the libraries listed below
Sorting:
- ☆27Updated 5 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago
- ☆29Updated 3 weeks ago
- ☆19Updated 2 weeks ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 6 months ago
- ☆29Updated 5 years ago
- ☆10Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- ☆13Updated 6 months ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- ☆13Updated this week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 5 months ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Network on Chip for MPSoC☆27Updated 3 months ago
- DUTH RISC-V Microprocessor☆20Updated 9 months ago
- ☆13Updated 10 years ago
- RISC-V IOMMU in verilog☆19Updated 3 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- ☆21Updated 5 years ago