CMU-SAFARI / MIG-7-PHY-DDR3-ControllerLinks
A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
☆11Updated 3 years ago
Alternatives and similar repositories for MIG-7-PHY-DDR3-Controller
Users that are interested in MIG-7-PHY-DDR3-Controller are comparing it to the libraries listed below
Sorting:
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 9 months ago
- ☆27Updated 5 years ago
- ☆28Updated 4 years ago
- ☆29Updated last month
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆20Updated 9 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- ☆20Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Development of a Network on Chip Simulation using SystemC.☆32Updated 7 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- Direct Access Memory for MPSoC☆12Updated last week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 8 months ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- Network on Chip for MPSoC☆26Updated last week
- ☆13Updated last week
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 5 years ago
- DUTH RISC-V Microprocessor☆20Updated 6 months ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 5 months ago