CMU-SAFARI / MIG-7-PHY-DDR3-Controller
A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
☆11Updated 3 years ago
Alternatives and similar repositories for MIG-7-PHY-DDR3-Controller:
Users that are interested in MIG-7-PHY-DDR3-Controller are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- ☆27Updated 4 years ago
- ☆27Updated 3 weeks ago
- verification of simple axi-based cache☆18Updated 5 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆20Updated 9 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆15Updated 4 years ago
- ☆21Updated 5 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- ☆25Updated last year
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- ☆20Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- DUTH RISC-V Microprocessor☆18Updated 5 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆40Updated 7 months ago
- RISC-V IOMMU in verilog☆17Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- SoC Based on ARM Cortex-M3☆30Updated this week
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- Direct Access Memory for MPSoC☆12Updated last week