shrut1996 / Cache-Implementation
Implementation of a cache memory in verilog
☆13Updated 7 years ago
Alternatives and similar repositories for Cache-Implementation:
Users that are interested in Cache-Implementation are comparing it to the libraries listed below
- A Verilog implementation of a processor cache.☆23Updated 7 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- ☆26Updated 5 years ago
- ☆24Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- ☆16Updated 2 years ago
- SoC Based on ARM Cortex-M3☆25Updated this week
- The memory model was leveraged from micron.☆22Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- ☆37Updated 2 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆40Updated 8 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- ☆40Updated 5 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- ☆25Updated 4 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆49Updated 3 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated this week
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆24Updated 3 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 7 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 6 months ago