PacoReinaCampo / vhdl2verilog
Hardware Description Language Translator
☆16Updated last month
Alternatives and similar repositories for vhdl2verilog:
Users that are interested in vhdl2verilog are comparing it to the libraries listed below
- AXI X-Bar☆19Updated 4 years ago
- Network on Chip for MPSoC☆26Updated 2 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- APB Logic☆15Updated 3 months ago
- Simple single-port AXI memory interface☆39Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated 2 weeks ago
- ☆24Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated this week
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Advanced Debug Interface☆14Updated 2 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆23Updated last month
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- Automatic SystemVerilog linting in github actions with the help of Verible☆33Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Hardware Description Language Translator☆17Updated last month
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆35Updated this week
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago