OSCPU / ysyx-examLinks
☆22Updated 2 years ago
Alternatives and similar repositories for ysyx-exam
Users that are interested in ysyx-exam are comparing it to the libraries listed below
Sorting:
- ☆92Updated 4 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆66Updated last year
- ☆90Updated 3 months ago
- ☆71Updated last week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆194Updated last year
- ☆64Updated 3 years ago
- ☆161Updated last month
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- Pick your favorite language to verify your chip.☆77Updated last week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- ☆19Updated 2 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- XiangShan Frontend Develop Environment☆68Updated this week
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆223Updated last week
- "aura" my super-scalar O3 cpu core☆25Updated last year
- ☆72Updated 2 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆74Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- ☆65Updated 5 years ago
- An exquisite superscalar RV32GC processor.☆165Updated last year
- Run rocket-chip on FPGA☆77Updated 2 months ago
- ☆220Updated last month
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆220Updated 7 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago