Alternatives and similar repositories for ysyx-exam:

Users that are interested in ysyx-exam are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆79Updated 3 weeks ago
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 7 months ago
• OSCPU / yosys-sta
  ☆57Updated 2 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆29Updated 11 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• leesum1 / ysyx
  一生一芯项目
  ☆11Updated last year
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆26Updated 2 years ago
• OSCPU / chisel-playground
  ☆63Updated last month
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆140Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆59Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆143Updated 4 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆22Updated last year
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆114Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆47Updated 4 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆39Updated this week
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆48Updated last year
• CherrySprings / CherrySprings
  ☆17Updated last year
• xiaoan109 / ysyx-workbench
  一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
  ☆17Updated last month
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆15Updated 5 years ago
• OSCPU / ysyx-workbench
  ☆138Updated 6 months ago
• RV-BOSC / OpenNoC
  ☆124Updated 2 weeks ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆124Updated 8 months ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆56Updated 3 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆93Updated 8 months ago
• OpenXiangShan / XS-Verilog-Library
  ☆40Updated 2 years ago