☆22Nov 25, 2023Updated 2 years ago
Alternatives and similar repositories for ysyx-exam
Users that are interested in ysyx-exam are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆99Oct 5, 2026Updated last week
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 3 years ago
- 我的一生一芯项目☆16Dec 14, 2021Updated 4 years ago
- ☆17Jul 23, 2025Updated last year
- Real Time GPA Calculator for Undergraduate Students in UCAS☆16Feb 22, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Undergraduate Course Materials in UCAS, from 2017 to 2021☆20Oct 12, 2020Updated 6 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆15Dec 4, 2025Updated 10 months ago
- RISC-V Open Source Supervisor Binary Interface☆10Jan 28, 2022Updated 4 years ago
- Hardware design with Chisel☆36Feb 9, 2023Updated 3 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆25May 22, 2025Updated last year
- ☆86Oct 5, 2026Updated last week
- Hardfloat using chisel3☆16Sep 23, 2020Updated 6 years ago
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated 2 months ago
- Community Add-on to the Adafruit_nRF52_Arduino Board Support Package☆17Oct 7, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- ☆126Jul 2, 2022Updated 4 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆54Mar 31, 2026Updated 6 months ago
- 一份面向UCAS本科计算机科学与技术专业同学的基础指南☆35Feb 1, 2023Updated 3 years ago
- Knowledge Graph of FPGA☆14Aug 21, 2021Updated 5 years ago
- ☆20Aug 23, 2025Updated last year
- A framework for ysyx flow☆14Oct 31, 2024Updated last year
- 电子科技大学的计算机组成原理实验课，并在此基础上实现了汇编编译器☆10Jun 14, 2022Updated 4 years ago
- Automated Repair of Verilog Hardware Descriptions☆39Jan 16, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V SoC designed by students in UCAS☆1,560Sep 22, 2026Updated 3 weeks ago
- ☆13Jul 21, 2026Updated 2 months ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆352Updated this week
- The YOLOv12 C++ TensorRT Project in C++ and optimized using NVIDIA TensorRT☆26Oct 22, 2025Updated 11 months ago
- Universal BLE/USB HID Library☆27Feb 25, 2023Updated 3 years ago
- a riscv32 rv32imc emulator written in c.☆33May 7, 2026Updated 5 months ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆22Mar 7, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 基于小脚丫FPGA的电子琴，模拟钢琴音色，支持127个音符演奏，可通过转化MIDI文件 实现自动播放☆19Aug 22, 2022Updated 4 years ago
- DDR2 memory controller written in Verilog☆86Feb 28, 2012Updated 14 years ago
- Scripts to automate building linux images for my emulator riscv_em☆16Jul 27, 2026Updated 2 months ago
- ☆28Oct 25, 2021Updated 4 years ago
- ☆25Apr 18, 2021Updated 5 years ago
- The decoder library for jemu execution and web documentation☆54Oct 6, 2023Updated 3 years ago
- The User Guide of XiangShan.☆22Sep 1, 2026Updated last month