ReuelReuben / vsdSRAMLinks
SRAM
☆23Updated 5 years ago
Alternatives and similar repositories for vsdSRAM
Users that are interested in vsdSRAM are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆77Updated 4 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- ☆42Updated 3 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- A configurable SRAM generator☆54Updated 3 weeks ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Open source process design kit for 28nm open process☆61Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- ☆35Updated 6 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- ☆20Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Python Tool for UVM Testbench Generation☆54Updated last year
- ☆27Updated 5 years ago
- Project repo for the POSH on-chip network generator☆50Updated 6 months ago