ReuelReuben / vsdSRAM
SRAM
☆22Updated 4 years ago
Alternatives and similar repositories for vsdSRAM:
Users that are interested in vsdSRAM are comparing it to the libraries listed below
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- ☆40Updated 3 years ago
- ☆26Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆26Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- ☆31Updated 5 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated last week
- ☆27Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆12Updated 9 months ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated last year
- ☆13Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆40Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆54Updated last month
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- ☆16Updated 2 years ago