ReuelReuben / vsdSRAMLinks
SRAM
☆22Updated 5 years ago
Alternatives and similar repositories for vsdSRAM
Users that are interested in vsdSRAM are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Open source process design kit for 28nm open process☆69Updated last year
- ☆43Updated 3 years ago
- A configurable SRAM generator☆56Updated 4 months ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- sram/rram/mram.. compiler☆43Updated 2 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆147Updated this week
- This is a tutorial on standard digital design flow☆81Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- ☆20Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 2 weeks ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆33Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Verilog RTL Design☆46Updated 4 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 4 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago