ReuelReuben / vsdSRAMLinks
SRAM
☆22Updated 4 years ago
Alternatives and similar repositories for vsdSRAM
Users that are interested in vsdSRAM are comparing it to the libraries listed below
Sorting:
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- ☆41Updated 3 years ago
- sram/rram/mram.. compiler☆37Updated last year
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- Open source process design kit for 28nm open process☆60Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆87Updated last year
- A configurable SRAM generator☆53Updated 3 weeks ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- ☆32Updated 7 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆73Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated 11 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆30Updated 2 weeks ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- ☆20Updated 3 years ago
- Python Tool for UVM Testbench Generation☆53Updated last year
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago