ReuelReuben / vsdSRAM
SRAM
☆21Updated 4 years ago
Alternatives and similar repositories for vsdSRAM:
Users that are interested in vsdSRAM are comparing it to the libraries listed below
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- ☆40Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆24Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- SKY130 SRAM macros generated by SRAM 22☆12Updated this week
- ☆31Updated last month
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆24Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- A configurable SRAM generator☆44Updated last month
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆14Updated 9 months ago
- Open source process design kit for 28nm open process☆48Updated 10 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆37Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- ☆29Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆43Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆16Updated 10 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- ☆12Updated 7 months ago