Alternatives and similar repositories for rtl-debugger

Users that are interested in rtl-debugger are comparing it to the libraries listed below

• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 8 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆38Updated 3 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆91Updated 8 months ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆47Updated last week
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆22Updated this week
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated last month
• RobertBaruch / amaranth-tutorial
  ☆41Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆22Updated 3 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆43Updated 3 weeks ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆92Updated 9 months ago
• Wren6991 / Hazard2
  Smol 2-stage RISC-V processor in nMigen
  ☆26Updated 4 years ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆17Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 5 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• TinyTapeout / tinytapeout_gds_viewer
  Tiny Tapeout GDS Online Viewer
  ☆19Updated 3 weeks ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 9 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated 3 weeks ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆85Updated last week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated last month
• 360nosc0pe / scope
  Siglent SDS1x0xX-E FPGA bitstreams
  ☆41Updated 5 months ago
• openXC7 / openXC7-snap
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆28Updated 11 months ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 2 years ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆41Updated last week
• regymm / GenZ
  The open-source Zynq 7000 BSP generator for openXC7
  ☆37Updated 5 months ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆48Updated 2 weeks ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆41Updated last month