Alternatives and similar repositories for rtl-debugger:

Users that are interested in rtl-debugger are comparing it to the libraries listed below

• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 6 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆18Updated 2 weeks ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆87Updated 7 months ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated last week
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆32Updated last year
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 7 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 2 weeks ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆40Updated 11 months ago
• daveshah1 / prjtrellis-dvi
  DVI video out example for prjtrellis
  ☆16Updated 6 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 7 months ago
• RobertBaruch / amaranth-tutorial
  ☆40Updated 2 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆16Updated 3 years ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆79Updated 2 weeks ago
• regymm / GenZ
  The open-source Zynq 7000 BSP generator for openXC7
  ☆25Updated 2 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 6 months ago
• Wren6991 / Hazard2
  Smol 2-stage RISC-V processor in nMigen
  ☆26Updated 3 years ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 3 months ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• kbob / nmigen-examples
  I want to learn [n]Migen.
  ☆40Updated 5 years ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆42Updated 3 weeks ago
• Wren6991 / TwoWireDebug
  Yet Another Debug Transport
  ☆20Updated 3 years ago
• lambdaconcept / lambdasoc
  ☆44Updated last month