nanocad-lab / CATCHLinks
CATCH 1.0, Initial full release of CATCH cost model.
☆16Updated 5 months ago
Alternatives and similar repositories for CATCH
Users that are interested in CATCH are comparing it to the libraries listed below
Sorting:
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 5 months ago
- ☆46Updated last year
- ☆54Updated 6 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆150Updated this week
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- An integrated CGRA design framework☆91Updated 9 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆165Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆71Updated 5 months ago
- A list of our chiplet simulaters☆46Updated 6 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 3 weeks ago
- ☆32Updated last year
- Dataset for ML-guided Accelerator Design☆43Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- The open-sourced version of BOOM-Explorer☆46Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last week
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆25Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- An Open-Source Tool for CGRA Accelerators☆28Updated 4 months ago
- ☆65Updated 8 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆197Updated 5 years ago
- ☆12Updated 3 months ago
- Public release☆58Updated 6 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆61Updated 9 months ago
- gem5 repository to study chiplet-based systems☆85Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- The first version of TritonPart☆31Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- ☆87Updated last year