google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0Links
9 track standard cells for GF180MCU provided by GlobalFoundries.
☆18Updated 2 years ago
Alternatives and similar repositories for globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
Users that are interested in globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 are comparing it to the libraries listed below
Sorting:
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆27Updated 2 years ago
- Primitives for SKY130 provided by SkyWater.☆27Updated last year
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆17Updated 2 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 3 years ago
- SRAM build space for SKY130 provided by SkyWater.☆22Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Extended and external tests for Verilator testing☆16Updated 3 weeks ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Primitives for GF180MCU provided by GlobalFoundries.☆53Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆47Updated 7 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- ☆43Updated 3 years ago
- ☆20Updated 3 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆25Updated 3 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Completed LDO Design for Skywaters 130nm☆16Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- ☆44Updated 5 years ago
- ☆38Updated 3 years ago
- Open Analog Design Environment☆24Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Open source process design kit for 28nm open process☆64Updated last year
- Characterizer☆30Updated 2 months ago
- Open Source PHY v2☆31Updated last year
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆14Updated 4 years ago