bespoke-silicon-group / bsg_sv2vView external linksLinks
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
☆44Apr 13, 2023Updated 2 years ago
Alternatives and similar repositories for bsg_sv2v
Users that are interested in bsg_sv2v are comparing it to the libraries listed below
Sorting:
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Jan 13, 2023Updated 3 years ago
- ☆14Feb 3, 2025Updated last year
- ☆10Apr 8, 2021Updated 4 years ago
- ☆14Jun 12, 2024Updated last year
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆14Feb 10, 2026Updated last week
- Fast Symbolic Repair of Hardware Design Code☆33Jan 20, 2025Updated last year
- SystemVerilog to Verilog conversion☆701Nov 24, 2025Updated 2 months ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 6 years ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆13Oct 24, 2017Updated 8 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- A RISC-V CPU implementation☆17Apr 9, 2020Updated 5 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 4 years ago
- ☆18Jul 9, 2025Updated 7 months ago
- CATCH 1.0, Initial full release of CATCH cost model.☆16Jul 22, 2025Updated 6 months ago
- Characterizer☆31Nov 19, 2025Updated 2 months ago
- AMC: Asynchronous Memory Compiler☆52Jun 29, 2020Updated 5 years ago
- ☆19Oct 28, 2024Updated last year
- Python Tool for UVM Testbench Generation☆55May 19, 2024Updated last year
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆22Oct 30, 2025Updated 3 months ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Feb 15, 2024Updated 2 years ago
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆25Jul 1, 2024Updated last year
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Jun 10, 2021Updated 4 years ago
- Circuit release of the MAGICAL project☆40Jan 10, 2020Updated 6 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 2 years ago
- ☆40Jun 13, 2015Updated 10 years ago
- SRAM☆22Sep 6, 2020Updated 5 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆13Sep 3, 2018Updated 7 years ago
- ☆11Jan 21, 2019Updated 7 years ago
- Tools for manipulating CHC and related files☆15Apr 21, 2023Updated 2 years ago
- work in progress, playing around with btor2 in rust☆12Updated this week
- DATC Robust Design Flow.☆36Jan 21, 2020Updated 6 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago