ucb-substrate / substrate2Links
21st century electronic design automation tools, written in Rust.
☆33Updated last week
Alternatives and similar repositories for substrate2
Users that are interested in substrate2 are comparing it to the libraries listed below
Sorting:
- Logic circuit analysis and optimization☆45Updated 4 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆103Updated last week
- An automatic clock gating utility☆51Updated 8 months ago
- design and verification of asynchronous circuits☆41Updated last month
- Equivalence checking with Yosys☆53Updated 2 weeks ago
- Hardware generator debugger☆77Updated last year
- A configurable SRAM generator☆56Updated 4 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆89Updated 2 weeks ago
- A SystemVerilog language server based on the Slang library.☆82Updated last week
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated 11 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆123Updated this week
- ☆59Updated 3 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆55Updated last year
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- A Verilog Filelist parser in Rust☆11Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- SystemVerilog frontend for Yosys☆181Updated last week
- ☆58Updated 8 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- ☆19Updated 2 months ago
- WAL enables programmable waveform analysis.☆163Updated last month
- Verilog AST☆21Updated 2 years ago
- ☆23Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆49Updated last year
- GL0AM GPU Accelerated Gate Level Logic Simulator☆29Updated 4 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- ☆33Updated 11 months ago