21st century electronic design automation tools, written in Rust.
☆36Mar 12, 2026Updated last week
Alternatives and similar repositories for substrate2
Users that are interested in substrate2 are comparing it to the libraries listed below
Sorting:
- ☆15Dec 9, 2025Updated 3 months ago
- A configurable SRAM generator☆58Mar 4, 2026Updated 2 weeks ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆15Mar 11, 2026Updated last week
- SKY130 SRAM macros generated by SRAM 22☆19Aug 19, 2025Updated 7 months ago
- Interchange formats for chip design.☆38Feb 15, 2026Updated last month
- ☆16Jan 25, 2026Updated last month
- Native Rust implementation of the FST waveform format from GTKWave.☆13Mar 12, 2026Updated last week
- ☆19Jul 12, 2024Updated last year
- ☆19Jan 2, 2026Updated 2 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Analyze experimental data with Programming by Navigation☆17Mar 8, 2026Updated last week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆109Mar 13, 2026Updated last week
- Website for CS 265☆33Dec 27, 2024Updated last year
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated 11 months ago
- ☆17Mar 26, 2025Updated 11 months ago
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆49Updated this week
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- design and verification of asynchronous circuits☆44Feb 27, 2026Updated 3 weeks ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆42Jul 17, 2024Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- Python interface for Cadence Spectre☆25Feb 17, 2026Updated last month
- Parametrized RTL benchmark suite☆25Feb 6, 2026Updated last month
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- Logic circuit analysis and optimization☆46Feb 2, 2026Updated last month
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆91Mar 5, 2026Updated 2 weeks ago
- SystemVerilog frontend for Yosys☆210Updated this week
- Integrated Circuit Layout☆58Feb 25, 2025Updated last year
- AMulet 2. - A better AIG Multiplier Examination Tool☆28Dec 23, 2025Updated 2 months ago
- Fearless hardware design☆198Aug 20, 2025Updated 7 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆26Apr 9, 2025Updated 11 months ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Dec 5, 2023Updated 2 years ago
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆46Apr 9, 2025Updated 11 months ago
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- ☆23Mar 5, 2026Updated 2 weeks ago