Alternatives and similar repositories for substrate2:

Users that are interested in substrate2 are comparing it to the libraries listed below

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 7 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• pulp-platform / svase
  ☆31Updated last month
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆23Updated last week
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆40Updated this week
• dan-fritchman / Layout21
  Integrated Circuit Layout
  ☆49Updated this week
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆32Updated 4 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆87Updated this week
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆35Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆71Updated 2 weeks ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆16Updated 4 years ago
• The-OpenROAD-Project / asap7
  ☆122Updated 6 months ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆44Updated this week
• rahulk29 / sram22_sky130_macros
  SKY130 SRAM macros generated by SRAM 22
  ☆11Updated 2 weeks ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• Ravenslofty / librecell
  ☆20Updated 3 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆43Updated 4 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆40Updated 3 months ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆56Updated 8 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 3 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆60Updated this week
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 3 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 6 months ago