jazvw / chip_artLinks
Convert an image to a GDS format for inclusion in a zerotoasic project
☆17Updated 3 years ago
Alternatives and similar repositories for chip_art
Users that are interested in chip_art are comparing it to the libraries listed below
Sorting:
- Characterizer☆31Updated 2 months ago
- Analog and power building blocks for sky130 pdk☆22Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- Yosys plugin for logic locking and supply-chain security☆23Updated 9 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆50Updated 10 months ago
- An example of analogue design using open source IC design tools☆29Updated 4 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated last month
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- Parasitic capacitance analysis of foundry metal stackups☆15Updated last week
- A set of rules and recommendations for analog and digital circuit designers.☆31Updated last year
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 5 years ago
- Open-source PDK version manager☆35Updated last month
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆64Updated 4 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆67Updated last month
- KLayout technology files for Skywater SKY130☆44Updated 2 years ago
- SpiceBind – spice inside HDL simulator☆56Updated 6 months ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆73Updated 4 years ago
- ☆26Updated 4 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- Fabric generator and CAD tools graphical frontend☆17Updated 5 months ago
- ☆13Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated last year
- Prefix tree adder space exploration library☆56Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- ☆38Updated 3 years ago
- ☆38Updated 3 years ago
- ☆59Updated 6 months ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆35Updated 10 months ago