jazvw / chip_artLinks
Convert an image to a GDS format for inclusion in a zerotoasic project
☆15Updated 3 years ago
Alternatives and similar repositories for chip_art
Users that are interested in chip_art are comparing it to the libraries listed below
Sorting:
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 5 months ago
- Characterizer☆30Updated last month
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated last month
- A set of rules and recommendations for analog and digital circuit designers.☆29Updated 10 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensour…☆16Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Open-source PDK version manager☆22Updated last week
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆10Updated 3 months ago
- Parasitic capacitance analysis of foundry metal stackups☆15Updated 4 months ago
- Repo to help explain the different options users have for packaging.☆18Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆44Updated 6 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆53Updated 3 months ago
- SAR ADC on tiny tapeout☆42Updated 7 months ago
- Online viewer of Xschem schematic files☆27Updated 9 months ago
- ☆39Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 11 months ago
- ☆12Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆29Updated 6 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- ☆30Updated 4 years ago
- Efabless mpw7 submission☆13Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆64Updated last week
- An example of analogue design using open source IC design tools☆29Updated 4 years ago