jazvw / chip_art

Related projects ⓘ

Alternatives and complementary repositories for chip_art

• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• hdl / packages
  Repo to help explain the different options users have for packaging.
  ☆16Updated 2 years ago
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆17Updated 3 years ago
• TinyTapeout / xschem-viewer
  Online viewer of Xschem schematic files
  ☆20Updated 3 months ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆19Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 10 months ago
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆20Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• snishizawa / libretto
  Characterizer
  ☆20Updated 2 months ago
• TheMightyDuckOfDoom / liberty74
  A Fully Open-Source Verilog-to-PCB Flow
  ☆17Updated 4 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆47Updated this week
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆37Updated 3 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated 3 weeks ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆17Updated 4 months ago
• yrrapt / caravel_amsat_txrx_ic
  ☆29Updated 3 years ago
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆14Updated 7 months ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆14Updated 3 months ago
• mattvenn / openlane_summary
  ☆19Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆34Updated this week
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆43Updated 3 months ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆18Updated 3 weeks ago
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆20Updated 3 months ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆35Updated this week
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆30Updated 8 months ago
• christoph-weiser / mpw7
  Efabless mpw7 submission
  ☆13Updated 6 months ago
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 3 years ago
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year
• iic-jku / Circuit-Designers-Etiquette
  A set of rules and recommendations for analog and digital circuit designers.
  ☆25Updated last week