jazvw / chip_artLinks
Convert an image to a GDS format for inclusion in a zerotoasic project
☆13Updated 3 years ago
Alternatives and similar repositories for chip_art
Users that are interested in chip_art are comparing it to the libraries listed below
Sorting:
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated 2 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated last week
- Yosys plugin for logic locking and supply-chain security☆22Updated 4 months ago
- Characterizer☆29Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- Online viewer of Xschem schematic files☆26Updated 7 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Repo to help explain the different options users have for packaging.☆17Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated this week
- An example of analogue design using open source IC design tools☆29Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆42Updated 4 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- SAR ADC on tiny tapeout☆42Updated 6 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- ☆38Updated 3 years ago
- Open-source PDK version manager☆18Updated last month
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆49Updated last month
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Parasitic capacitance analysis of foundry metal stackups☆15Updated 3 months ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- Library of reusable VHDL components☆28Updated last year
- Fabric generator and CAD tools graphical frontend☆13Updated this week