Alternatives and similar repositories for OpenSRAM

Users that are interested in OpenSRAM are comparing it to the libraries listed below

• rahulk29 / sram22
  A configurable SRAM generator
  ☆57Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 10 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆67Updated last year
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆33Updated 4 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆43Updated 2 years ago
• vsdip / vsdsram
  An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…
  ☆12Updated 5 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆137Updated last week
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆31Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆32Updated this week
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆35Updated last year
• chiselverify / vhdl2verilog
  ☆17Updated 5 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆34Updated 4 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆26Updated 6 years ago
• vsdip / avsddac_3v3_sky130_v1
  ☆12Updated 3 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 5 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆37Updated 7 years ago