SRAM Design using OpenSource Applications
☆24Jul 16, 2021Updated 4 years ago
Alternatives and similar repositories for OpenSRAM
Users that are interested in OpenSRAM are comparing it to the libraries listed below
Sorting:
- SRAM☆22Sep 6, 2020Updated 5 years ago
- sram/rram/mram.. compiler☆48Sep 11, 2023Updated 2 years ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆16Apr 28, 2021Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- A configurable SRAM generator☆58Mar 4, 2026Updated 2 weeks ago
- Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis☆17Dec 9, 2022Updated 3 years ago
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 4 years ago
- A C++ -based STIL parser.☆12Apr 29, 2021Updated 4 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82May 2, 2021Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆18Jul 21, 2020Updated 5 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Open and View your Notability note file (*.note) on Windows☆12May 11, 2023Updated 2 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- ☆14Mar 9, 2026Updated last week
- ☆11Jan 21, 2019Updated 7 years ago
- An open-source static random access memory (SRAM) compiler.☆1,021Mar 12, 2026Updated last week
- RISC-V Processor written in Amaranth HDL☆39Jan 21, 2022Updated 4 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆41Mar 2, 2022Updated 4 years ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- Copyleftist's Standard Cell Library☆101May 2, 2024Updated last year
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- kenDryte K210 Cloud Build Support☆11Oct 24, 2018Updated 7 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated this week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Jul 12, 2024Updated last year
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- Superscalar Out-of-Order NPU Design on FPGA☆12May 17, 2024Updated last year
- ☆13Feb 9, 2023Updated 3 years ago
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Embedding billion-scale networks accurately in one hour (TKDE paper 2023)☆11Sep 26, 2023Updated 2 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆24Nov 15, 2021Updated 4 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆25Updated this week
- A command-line tool for convert SVG image to PDF file☆17Mar 29, 2025Updated 11 months ago