iamkrvikash / OpenSRAMLinks
SRAM Design using OpenSource Applications
☆22Updated 4 years ago
Alternatives and similar repositories for OpenSRAM
Users that are interested in OpenSRAM are comparing it to the libraries listed below
Sorting:
- A configurable SRAM generator☆54Updated last month
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- Open source process design kit for 28nm open process☆61Updated last year
- sram/rram/mram.. compiler☆42Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- ☆38Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 7 months ago
- SRAM☆22Updated 5 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- ☆42Updated 3 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last month
- ☆17Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- ☆33Updated 2 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated 11 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated last month
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆21Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- ☆19Updated last year
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆24Updated 6 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 6 months ago