Alternatives and similar repositories for sa-placer

Users that are interested in sa-placer are comparing it to the libraries listed below

• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆64Updated last week
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆31Updated last year
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆42Updated 3 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 9 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆94Updated last month
• oxidecomputer / quartz
  Soft-logic designs and HAL libraries for various subsystems found in Oxide hardware.
  ☆16Updated this week
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated last year
• amaranth-lang / playground
  Playground for experimenting with and sharing short Amaranth programs on the web
  ☆20Updated 3 months ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆19Updated 3 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 4 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆76Updated this week
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆44Updated 5 months ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• amaranth-lang / amaranth-yosys
  WebAssembly-based Yosys distribution for Amaranth HDL
  ☆29Updated last week
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆39Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆81Updated last week
• lethalbit / discretize
  A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
  ☆13Updated 2 years ago
• regymm / GenZ
  The open-source Zynq 7000 BSP generator for openXC7
  ☆51Updated last year
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆13Updated last week
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last year
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆42Updated 2 weeks ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆63Updated 6 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 5 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 months ago