stefanpie / sa-placerLinks
☆16Updated last year
Alternatives and similar repositories for sa-placer
Users that are interested in sa-placer are comparing it to the libraries listed below
Sorting:
- An FPGA reverse engineering and documentation project☆58Updated last week
- Industry standard I/O for Amaranth HDL☆30Updated last year
- Hot Reconfiguration Technology demo☆40Updated 3 years ago
- Exploring gate level simulation☆58Updated 6 months ago
- End-to-end synthesis and P&R toolchain☆89Updated last month
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated this week
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated 10 months ago
- System on Chip toolkit for Amaranth HDL☆95Updated last year
- RISC-V out-of-order core for education and research purposes☆65Updated 3 weeks ago
- Playground for experimenting with and sharing short Amaranth programs on the web☆16Updated this week
- PicoRV☆43Updated 5 years ago
- 妖刀夢渡☆63Updated 6 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆18Updated 2 years ago
- Soft-logic designs and HAL libraries for various subsystems found in Oxide hardware.☆14Updated this week
- Logic circuit analysis and optimization☆42Updated 2 months ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆13Updated last year
- Another size-optimized RISC-V CPU for your consideration.☆57Updated 3 weeks ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated 6 months ago
- Unofficial Yosys WebAssembly packages☆73Updated this week
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- chipy hdl☆17Updated 7 years ago
- design and verification of asynchronous circuits☆41Updated 2 weeks ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆28Updated this week
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago