stefanpie / sa-placerLinks
☆16Updated last year
Alternatives and similar repositories for sa-placer
Users that are interested in sa-placer are comparing it to the libraries listed below
Sorting:
- An FPGA reverse engineering and documentation project☆58Updated 2 weeks ago
- Industry standard I/O for Amaranth HDL☆30Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Exploring gate level simulation☆58Updated 6 months ago
- Hot Reconfiguration Technology demo☆41Updated 3 years ago
- Logic circuit analysis and optimization☆42Updated 2 months ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- RISC-V out-of-order core for education and research purposes☆76Updated last week
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- End-to-end synthesis and P&R toolchain☆90Updated last month
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆13Updated last year
- design and verification of asynchronous circuits☆41Updated last month
- PicoRV☆43Updated 5 years ago
- chipy hdl☆17Updated 7 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆18Updated 2 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- Soft-logic designs and HAL libraries for various subsystems found in Oxide hardware.☆15Updated this week
- A collection of little open source FPGA hobby projects☆50Updated 5 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated last week
- A Verilog Synthesis Regression Test☆37Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Native Rust implementation of the FST waveform format from GTKWave.☆13Updated 2 months ago
- Playground for experimenting with and sharing short Amaranth programs on the web☆19Updated 2 weeks ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated 11 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- 21st century electronic design automation tools, written in Rust.☆32Updated this week