pulp-platform / cv32e40pLinks
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
☆19Updated this week
Alternatives and similar repositories for cv32e40p
Users that are interested in cv32e40p are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆53Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- Advanced Architecture Labs with CVA6☆65Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- ☆96Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- ☆34Updated 6 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆64Updated 4 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆22Updated last year
- BlackParrot on Zynq☆43Updated 4 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆168Updated 7 months ago
- A Fast, Low-Overhead On-chip Network☆214Updated last week
- Two Level Cache Controller implementation in Verilog HDL☆49Updated 5 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- This is the fork of CVA6 intended for PULP development.☆21Updated this week
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- ☆51Updated 6 years ago
- A demo system for Ibex including debug support and some peripherals☆73Updated last month
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- HYF's high quality verilog codes☆13Updated 6 months ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆24Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago