pulp-platform / cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
☆19Updated last month
Alternatives and similar repositories for cv32e40p:
Users that are interested in cv32e40p are comparing it to the libraries listed below
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Advanced Architecture Labs with CVA6☆57Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆54Updated last month
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated this week
- ☆43Updated 6 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- ☆92Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆42Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- BlackParrot on Zynq☆38Updated last month
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆27Updated 4 years ago
- ☆31Updated 5 years ago
- This is the fork of CVA6 intended for PULP development.☆19Updated last week
- Xilinx AXI VIP example of use☆37Updated 3 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- SoC Based on ARM Cortex-M3☆30Updated 2 weeks ago
- ☆54Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆59Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 6 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- ☆49Updated 2 years ago