CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
☆20Mar 11, 2026Updated last week
Alternatives and similar repositories for cv32e40p
Users that are interested in cv32e40p are comparing it to the libraries listed below
Sorting:
- This is the fork of CVA6 intended for PULP development.☆22Mar 14, 2026Updated last week
- RISC-V fast interrupt controller☆33Nov 20, 2025Updated 4 months ago
- Neural Engine, 16 input channels☆16Oct 31, 2022Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 2 months ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Jan 9, 2026Updated 2 months ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Sep 9, 2025Updated 6 months ago
- Mirror of the now discontinued ORCA RISC-V processor from VectorBlox.☆10Feb 11, 2020Updated 6 years ago
- ☆10Nov 12, 2019Updated 6 years ago
- ☆14Mar 9, 2026Updated last week
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- ☆15Apr 17, 2022Updated 3 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 3 months ago
- RISC-V RV32IMAFC Core for MCU☆42Feb 1, 2025Updated last year
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- Ocamlgraph overlay for llvm☆20Apr 4, 2015Updated 10 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated last year
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆21Mar 16, 2026Updated last week
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- ☆14Jan 22, 2026Updated 2 months ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- A vector graphics renderer for bgfx, based on ideas from NanoVG and ImDrawList (Dear ImGUI)☆10Feb 11, 2026Updated last month
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆60Mar 10, 2026Updated last week
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- Coverview☆28Jan 29, 2026Updated last month
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Mar 14, 2026Updated last week
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- Toy RISC-V emulator☆15Oct 10, 2017Updated 8 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆14Nov 12, 2025Updated 4 months ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- General Purpose IO with APB4 interface☆15May 10, 2024Updated last year
- ☆11Feb 16, 2019Updated 7 years ago