pulp-platform / cv32e40p

Related projects ⓘ

Alternatives and complementary repositories for cv32e40p

• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 5 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• chipsalliance / uvm-verilator
  ☆73Updated last year
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆44Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆22Updated last month
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆43Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆48Updated 9 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆58Updated last week
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆19Updated 2 weeks ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆54Updated 2 months ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆25Updated last week
• pulp-platform / fpu
  ☆37Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆47Updated 4 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆134Updated 2 weeks ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆19Updated 6 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆11Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated 2 weeks ago
• wanderingnail / AXI_DMA
  ☆15Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆57Updated 3 weeks ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆54Updated 3 years ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆14Updated 2 months ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆27Updated 2 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆26Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆18Updated 6 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆44Updated 5 years ago