pulp-platform / cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
☆19Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for cv32e40p
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- DUTH RISC-V Microprocessor☆19Updated 2 weeks ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- ☆75Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆45Updated 3 years ago
- ☆26Updated 5 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago
- ☆25Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- This is the fork of CVA6 intended for PULP development.☆16Updated this week
- A demo system for Ibex including debug support and some peripherals☆55Updated 3 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated 3 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- [UNRELEASED] FP div/sqrt unit for transprecision☆18Updated 7 months ago
- Two Level Cache Controller implementation in Verilog HDL☆36Updated 4 years ago
- ☆16Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- The memory model was leveraged from micron.☆19Updated 6 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆69Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- A Fast, Low-Overhead On-chip Network☆140Updated this week
- round robin arbiter☆68Updated 10 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago