AlessandroCilardo / NaplesPULinks
The official NaplesPU hardware code repository
☆20Updated 6 years ago
Alternatives and similar repositories for NaplesPU
Users that are interested in NaplesPU are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated this week
- ☆33Updated last month
- Chisel implementation of Neural Processing Unit for System on the Chip☆25Updated 4 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆21Updated 2 weeks ago
- matrix-coprocessor for RISC-V☆26Updated 2 weeks ago
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- ☆20Updated last week
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆19Updated 9 months ago
- ☆31Updated 5 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆19Updated 8 months ago
- HLS for Networks-on-Chip☆38Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Updated 10 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆31Updated last week
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆28Updated 6 years ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- ☆57Updated 6 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 7 months ago