Alternatives and similar repositories for NaplesPU:

Users that are interested in NaplesPU are comparing it to the libraries listed below

• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 6 months ago
• pulp-platform / axi_llc
  ☆26Updated 2 weeks ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 2 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆34Updated last year
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆14Updated this week
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆14Updated 6 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆34Updated last month
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆18Updated 8 months ago
• m-asiatici / MSHR-rich
  A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…
  ☆19Updated 4 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆18Updated last week
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated last month
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆14Updated 2 months ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆31Updated 4 months ago
• nullromo / compression-accelerator
  Implementation of the Snappy compression algorithm as a RoCC accelerator
  ☆11Updated 5 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 2 weeks ago
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆17Updated 2 weeks ago
• pulp-platform / ace
  ☆11Updated last month
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆25Updated 2 weeks ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆27Updated 6 months ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆17Updated 3 weeks ago
• chipsalliance / tilelink
  ☆30Updated 4 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆39Updated 2 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• sequencer / arithmetic
  ☆33Updated last month