halftop / Interface-Protocol-in-VerilogLinks
Interface Protocol in Verilog
☆51Updated 6 years ago
Alternatives and similar repositories for Interface-Protocol-in-Verilog
Users that are interested in Interface-Protocol-in-Verilog are comparing it to the libraries listed below
Sorting:
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- ☆38Updated 10 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- AHB DMA 32 / 64 bits☆58Updated 11 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated 2 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Updated 6 years ago
- ☆34Updated 6 years ago
- Verilog SPI master and slave☆62Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- AXI Interconnect☆56Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆39Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- ☆74Updated 10 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆39Updated 8 years ago
- AXI4 BFM in Verilog☆35Updated 9 years ago
- round robin arbiter☆77Updated 11 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆64Updated 3 years ago
- ☆20Updated 3 years ago
- Generic AXI to AHB bridge☆18Updated 11 years ago