☆27Jun 12, 2022Updated 3 years ago
Alternatives and similar repositories for dma-bench
Users that are interested in dma-bench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open source FPGA-based NIC and platform for in-network compute☆68Aug 21, 2025Updated 9 months ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- ☆15Apr 18, 2023Updated 3 years ago
- PCI express simulation framework for Cocotb☆204Sep 8, 2025Updated 8 months ago
- Ethernet interface modules for Cocotb☆78Sep 8, 2025Updated 8 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Ethernet switch implementation written in Verilog☆65Jun 13, 2023Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- PyTorch Quantization Framework For OCP MX Datatypes.☆16May 30, 2025Updated 11 months ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- C++ reference implementation for Push-In First-Out Queue☆15Aug 18, 2016Updated 9 years ago
- Open FPGA Modules☆25Oct 8, 2024Updated last year
- ☆12Aug 26, 2016Updated 9 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- ☆35Mar 8, 2023Updated 3 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verilog-Based-NoC-Simulator☆11May 4, 2016Updated 10 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- ☆14May 15, 2023Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆61Dec 31, 2019Updated 6 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 7 years ago
- An OpenFlow implementation for the NetFPGA-10G card☆19Feb 18, 2015Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- AXI interface modules for Cocotb☆331Mar 13, 2026Updated 2 months ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated this week
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Direct Access Memory for MPSoC☆13Updated this week
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- ☆14Feb 24, 2025Updated last year
- ☆29May 11, 2021Updated 5 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago