☆13Jul 2, 2016Updated 9 years ago
Alternatives and similar repositories for Verilog-Matrix-multiply-vector
Users that are interested in Verilog-Matrix-multiply-vector are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated this week
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Sep 3, 2019Updated 6 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Oct 24, 2014Updated 11 years ago
- CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.☆12Jun 19, 2020Updated 5 years ago
- Motion detection in both software and in hardware-accelerated OpenCV☆15Dec 26, 2016Updated 9 years ago
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 7 years ago
- Integration of SIFT and LES Algorithms☆14May 6, 2024Updated 2 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 9 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆133May 4, 2026Updated 3 weeks ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆28Mar 11, 2019Updated 7 years ago
- PyTorch implementation of Towards Efficient Training for Neural Network Quantization☆16Jan 16, 2020Updated 6 years ago
- [AAAI 2025] Official data and code for "TB-HSU: Hierarchical 3D Scene Understanding with Contextual Affordances"☆15Sep 11, 2025Updated 8 months ago
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago
- ☆11Aug 2, 2024Updated last year
- 一个基于AXI接口的PL端卷积加速器，可由PS端调用☆12Apr 15, 2023Updated 3 years ago
- Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision☆12Jan 19, 2026Updated 4 months ago
- Design for 4 x 4 Matrix Multiplication using Verilog☆34Jun 9, 2015Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆21Mar 5, 2023Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆56Aug 12, 2017Updated 8 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Quantize pytorch model, support post-training quantization and quantization aware training methods☆14Jun 15, 2023Updated 2 years ago
- ☆37Jun 19, 2023Updated 2 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated last year
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 7 years ago
- AES128 is a IP crypto core using modes ECB/CBC/CTR using vpi to functional verification☆18Mar 31, 2023Updated 3 years ago
- Source code of basic Xilinx Vivado HLS image processing tutorial using HLS openCV functions☆26Jul 7, 2018Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆123Apr 3, 2026Updated last month