pulp-platform / ne16Links
Neural Engine, 16 input channels
☆13Updated 2 years ago
Alternatives and similar repositories for ne16
Users that are interested in ne16 are comparing it to the libraries listed below
Sorting:
- ☆33Updated 2 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆25Updated this week
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated last year
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 10 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- APB Logic☆18Updated 5 months ago
- Pulp virtual platform☆23Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- ☆29Updated last month
- The multi-core cluster of a PULP system.☆97Updated this week
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- ☆81Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Open-Source HLS Examples for Microchip FPGAs☆44Updated this week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated 2 weeks ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- BlackParrot on Zynq☆41Updated 3 months ago
- Tutorials on HLS Design☆51Updated 5 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆43Updated last month
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year