Synthesisable SIMT-style RISC-V GPGPU
☆49Jul 7, 2025Updated 7 months ago
Alternatives and similar repositories for SIMTight
Users that are interested in SIMTight are comparing it to the libraries listed below
Sorting:
- ☆17May 9, 2022Updated 3 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Apr 14, 2025Updated 10 months ago
- RISC-V BSV Specification☆23Jan 18, 2020Updated 6 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated last month
- ☆17Mar 17, 2022Updated 3 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆32Dec 24, 2025Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆54Apr 11, 2020Updated 5 years ago
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。☆22Nov 24, 2024Updated last year
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Learn NVDLA by SOMNIA☆42Dec 13, 2019Updated 6 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Aug 29, 2023Updated 2 years ago
- ☆22Nov 3, 2025Updated 4 months ago
- ☆64Sep 23, 2022Updated 3 years ago
- Ratatoskr NoC Simulator☆29Apr 13, 2021Updated 4 years ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆44Updated this week
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Vijos: Vijos Isn't Just an Operating System☆10May 31, 2020Updated 5 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- ☆13May 8, 2025Updated 9 months ago
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 4 months ago
- Superscalar Out-of-Order NPU Design on FPGA☆11May 17, 2024Updated last year
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆13Jun 7, 2025Updated 8 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated last month
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆34Updated this week
- A Toy-Purpose TPU Simulator☆22Jun 7, 2024Updated last year