CTSRD-CHERI / SIMTightLinks
Synthesisable SIMT-style RISC-V GPGPU
☆39Updated 3 weeks ago
Alternatives and similar repositories for SIMTight
Users that are interested in SIMTight are comparing it to the libraries listed below
Sorting:
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last month
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- Wrappers for open source FPU hardware implementations.☆33Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- ☆71Updated last week
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆107Updated 2 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Intel Compiler for SystemC☆24Updated 2 years ago
- The official NaplesPU hardware code repository☆17Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated this week
- Various examples for Chisel HDL☆30Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated last week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated 2 months ago
- ☆37Updated last year
- A Rocket-based RISC-V superscalar in-order core☆34Updated 3 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago