ted-xie / REAPRLinks
REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions. REAPR is currently only compatible with SDAccel-capable Xilinx FPGA boards.
☆16Updated 5 years ago
Alternatives and similar repositories for REAPR
Users that are interested in REAPR are comparing it to the libraries listed below
Sorting:
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Updated 9 years ago
- Useful utilities for BAR projects☆31Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- DyRACT Open Source Repository☆16Updated 9 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- ☆56Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- A home for Genesis2 sources.☆42Updated 3 weeks ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- 🔁 elastic circuit toolchain☆31Updated 6 months ago
- Caribou: Distributed Smart Storage built with FPGAs☆67Updated 6 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- ☆11Updated 3 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆14Updated 2 years ago
- SmartNIC☆14Updated 6 years ago
- ☆23Updated 3 years ago
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago