Alternatives and similar repositories for REAPR

Users that are interested in REAPR are comparing it to the libraries listed below

• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆67Updated 7 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• FelixWinterstein / LEAP-HLS
  Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework
  ☆12Updated 9 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 2 months ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆39Updated 2 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆42Updated last month
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆50Updated 2 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• drom / reqack
  🔁 elastic circuit toolchain
  ☆31Updated 8 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 10 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 9 years ago