ted-xie / REAPRLinks
REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions. REAPR is currently only compatible with SDAccel-capable Xilinx FPGA boards.
☆16Updated 6 years ago
Alternatives and similar repositories for REAPR
Users that are interested in REAPR are comparing it to the libraries listed below
Sorting:
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Updated 9 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Caribou: Distributed Smart Storage built with FPGAs☆67Updated 7 years ago
- ☆56Updated 3 years ago
- OmniXtend cache coherence protocol☆82Updated 4 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- Useful utilities for BAR projects☆32Updated last year
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs☆18Updated 7 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- OpenFPGA☆33Updated 7 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆14Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago