pulp-platform / stream-ebpcLinks
Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.
☆24Updated 5 years ago
Alternatives and similar repositories for stream-ebpc
Users that are interested in stream-ebpc are comparing it to the libraries listed below
Sorting:
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- ☆72Updated 2 years ago
- ☆71Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 5 months ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- ☆63Updated 5 years ago
- ☆37Updated 4 years ago
- ☆35Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- ☆38Updated 8 months ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- ☆30Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Eyeriss chip simulator☆39Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- CNN accelerator☆27Updated 8 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆22Updated 3 years ago
- ☆85Updated 2 years ago