Alternatives and similar repositories for stream-ebpc:

Users that are interested in stream-ebpc are comparing it to the libraries listed below

• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 weeks ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆69Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• Kareem-Emad / DCNN-Accelerator
  Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
  ☆12Updated 5 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago
• hyoukjun / microswitch-noc
  ☆25Updated 5 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆29Updated last year
• sharc-lab / FPGA_ECE8893
  ☆33Updated last week
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆63Updated 3 years ago
• iitm-sysdl / FuSeConv
  Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021
  ☆14Updated 3 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 7 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆33Updated 5 months ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 4 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆86Updated 5 months ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆27Updated 6 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆34Updated 4 years ago
• alibaba / vector-accelerating-unit
  vector accelerating unit
  ☆26Updated 4 years ago
• VeriGOOD-ML / public
  ☆57Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆55Updated 3 years ago