Control and status register code generator toolchain
☆190Apr 16, 2026Updated 2 weeks ago
Alternatives and similar repositories for PeakRDL
Users that are interested in PeakRDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆79Mar 28, 2026Updated last month
- SystemRDL 2.0 language compiler front-end☆277Apr 10, 2026Updated 3 weeks ago
- Generate address space documentation HTML from compiled SystemRDL input☆62Mar 6, 2026Updated last month
- Code generation tool for control and status registers☆455Apr 19, 2026Updated last week
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generate UVM register model from compiled SystemRDL input☆61Nov 25, 2025Updated 5 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- ☆15Mar 28, 2026Updated last month
- C++ 17 Hardware abstraction layer generator from systemrdl☆15Apr 12, 2026Updated 2 weeks ago
- Control and Status Register map generator for HDL projects☆136May 24, 2025Updated 11 months ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- general-cores☆21Jul 16, 2025Updated 9 months ago
- An open-source HDL register code generator fast enough to run in real time.☆87Apr 20, 2026Updated last week
- The UVM written in Python☆534Apr 20, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog Logger☆19Apr 6, 2026Updated 3 weeks ago
- Python-based IP-XACT parser and utilities☆143Jun 13, 2024Updated last year
- cocotb: Python-based chip (RTL) verification☆2,339Apr 24, 2026Updated last week
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 5 months ago
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 2 months ago
- A dependency management tool for hardware projects.☆365Apr 22, 2026Updated last week
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆96Feb 26, 2026Updated 2 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆822Apr 22, 2026Updated last week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆19Updated this week
- An abstraction library for interfacing EDA tools☆762Apr 24, 2026Updated last week
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 4 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆144Apr 9, 2026Updated 3 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆203Apr 20, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆80Oct 22, 2024Updated last year
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆429Apr 22, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)☆18Aug 16, 2021Updated 4 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆39Apr 13, 2026Updated 2 weeks ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆147Mar 29, 2026Updated last month
- git clone of http://code.google.com/p/axi-bfm/☆18May 21, 2013Updated 12 years ago
- ☆15Mar 9, 2026Updated last month
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago