SystemRDL / PeakRDL
Control and status register code generator toolchain
☆128Updated last week
Alternatives and similar repositories for PeakRDL:
Users that are interested in PeakRDL are comparing it to the libraries listed below
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated this week
- Control and Status Register map generator for HDL projects☆116Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated 2 weeks ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆199Updated 6 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆113Updated last year
- ☆155Updated 2 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated 6 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆51Updated last week
- UVM 1.2 port to Python☆250Updated 2 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆163Updated this week
- ☆200Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- Generate UVM register model from compiled SystemRDL input☆54Updated 8 months ago
- RISC-V Verification Interface☆89Updated 2 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆38Updated 3 months ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆155Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆63Updated this week
- Python-based IP-XACT parser☆130Updated 10 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 3 months ago
- ☆92Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆59Updated 3 years ago
- SystemRDL 2.0 language compiler front-end☆251Updated last month
- ☆50Updated 8 years ago
- A complete open-source design-for-testing (DFT) Solution☆149Updated 6 months ago
- ☆82Updated 8 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆199Updated this week
- FuseSoC standard core library☆134Updated last month
- Announcements related to Verilator☆39Updated 4 years ago
- Playing around with Formal Verification of Verilog and VHDL☆56Updated 4 years ago