Alternatives and similar repositories for redundancy_cells

Users that are interested in redundancy_cells are comparing it to the libraries listed below

• pulp-platform / axi_llc
  ☆32Updated last week
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆32Updated this week
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated last month
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆24Updated 7 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 11 months ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago
• bsc-loca / mmu
  ☆13Updated 6 months ago
• pulp-platform / apb
  APB Logic
  ☆22Updated 3 weeks ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆34Updated 6 months ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆30Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 3 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• pulp-platform / ace
  ☆20Updated last month
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 6 years ago
• chipsalliance / aib-protocols
  ☆28Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆42Updated 2 years ago