Alternatives and similar repositories for ptrng

Users that are interested in ptrng are comparing it to the libraries listed below

• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆73Updated 2 months ago
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆19Updated 3 weeks ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆17Updated 5 years ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆46Updated this week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆127Updated 2 weeks ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆61Updated last year
• CommonEvaluationPlatform / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…
  ☆23Updated 10 months ago
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 2 weeks ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆62Updated 3 weeks ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆45Updated 3 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 3 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆193Updated this week
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆159Updated 3 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆87Updated last year
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆104Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 2 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆77Updated 2 months ago
• fpgaemu / fpgaemu
  Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…
  ☆49Updated 3 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 6 months ago
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆34Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆63Updated 6 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆68Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 7 months ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆71Updated 5 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆148Updated this week
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆44Updated 5 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆58Updated 2 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆103Updated this week
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆56Updated 2 months ago