opentrng / ptrngLinks
Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.
☆13Updated 3 months ago
Alternatives and similar repositories for ptrng
Users that are interested in ptrng are comparing it to the libraries listed below
Sorting:
- Extracts specified data from a VCD file into CSV form☆10Updated 6 years ago
- ☆11Updated 8 months ago
- IOPMP IP☆21Updated 6 months ago
- HW Design Collateral for Caliptra RoT IP☆124Updated last week
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated last week
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 6 years ago
- SystemVerilog frontend for Yosys☆186Updated last week
- A demo system for Ibex including debug support and some peripherals☆85Updated 2 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆59Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- My notes for DDR3 SDRAM controller☆43Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated last month
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆66Updated last year
- The OpenPiton Platform☆17Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated 3 months ago
- Advanced Architecture Labs with CVA6☆72Updated 2 years ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆53Updated this week
- The purpose of the repo is to support CORE-V Wally architectural verification☆16Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆155Updated 2 weeks ago
- RISC-V Nox core☆71Updated 5 months ago
- An automatic clock gating utility☆51Updated 9 months ago
- Fabric generator and CAD tools.☆214Updated 2 weeks ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆72Updated 3 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago