Alternatives and similar repositories for ptrng

Users that are interested in ptrng are comparing it to the libraries listed below

• ZSusskind / vcd2csv
  Extracts specified data from a VCD file into CSV form
  ☆10Updated 5 years ago
• socsecresearch / SoC_Vulnerability_Benchmarks
  ☆11Updated 8 months ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆48Updated this week
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated last month
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 5 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated 2 weeks ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆124Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• siliconcompiler / lambdalib
  Hardware abstraction library
  ☆43Updated last week
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆17Updated 6 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆143Updated last week
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 2 months ago
• BLu85 / AES-GCM-128-192-256-bits
  Configurable AES-GCM IP (128, 192, 256 bits)
  ☆38Updated 4 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated last month
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…
  ☆51Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆79Updated last week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆70Updated 3 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆21Updated last week
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆184Updated this week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆96Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 8 months ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 11 months ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆75Updated last week
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆98Updated last year
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago