Coloquinte / moosic-yosys-pluginLinks
Yosys plugin for logic locking and supply-chain security
☆22Updated 6 months ago
Alternatives and similar repositories for moosic-yosys-plugin
Users that are interested in moosic-yosys-plugin are comparing it to the libraries listed below
Sorting:
- Characterizer☆30Updated 2 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆47Updated 7 months ago
- An automatic clock gating utility☆51Updated 6 months ago
- ☆14Updated 5 months ago
- SpiceBind – spice inside HDL simulator☆56Updated 4 months ago
- UART cocotb module☆11Updated 4 years ago
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated last week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆19Updated 3 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆10Updated 5 months ago
- Open Source Verification Bundle for VHDL and System Verilog☆47Updated last year
- Parasitic capacitance analysis of foundry metal stackups☆15Updated 5 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆16Updated 3 years ago
- ☆33Updated 9 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆29Updated 2 months ago
- Open-source PDK version manager☆27Updated 3 weeks ago
- A configurable SRAM generator☆56Updated 2 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 3 months ago
- ☆57Updated 7 months ago
- ☆38Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆17Updated 2 years ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆11Updated last week
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago