Alternatives and similar repositories for icsprout55-pdk

Users that are interested in icsprout55-pdk are comparing it to the libraries listed below

• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆81Updated 4 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆70Updated last year
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆43Updated 2 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆78Updated 5 years ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆48Updated this week
• pulp-platform / svase
  ☆33Updated 11 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆21Updated 2 weeks ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆96Updated last year
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆22Updated last year
• OS-EDA / Course
  Home of the open-source EDA course.
  ☆52Updated 6 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 9 months ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆81Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆50Updated 4 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated 3 weeks ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• The-OpenROAD-Project / megaboom
  ☆33Updated last month
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆69Updated 3 years ago