openecos-projects / icsprout55-pdkLinks
55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
☆141Updated last week
Alternatives and similar repositories for icsprout55-pdk
Users that are interested in icsprout55-pdk are comparing it to the libraries listed below
Sorting:
- Open source process design kit for 28nm open process☆68Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated last week
- ☆43Updated 3 years ago
- A configurable SRAM generator☆56Updated 3 months ago
- ☆33Updated 11 months ago
- Making cocotb testbenches that bit easier☆36Updated last month
- Home of the open-source EDA course.☆50Updated 6 months ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- sram/rram/mram.. compiler☆43Updated 2 years ago
- SRAM☆22Updated 5 years ago
- ideas and eda software for vlsi design☆50Updated this week
- ☆58Updated 8 months ago
- SystemVerilog RTL Linter for YoSys☆21Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆95Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆169Updated this week
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆19Updated 4 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆77Updated 5 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- SystemVerilog frontend for Yosys☆178Updated this week
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆49Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- Characterizer☆30Updated 3 weeks ago
- RISC-V Nox core☆69Updated 4 months ago
- SystemVerilog Linter based on pyslang☆31Updated 7 months ago