iic-jku / IIC-OSIC-TOOLS
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
☆478Updated this week
Alternatives and similar repositories for IIC-OSIC-TOOLS
Users that are interested in IIC-OSIC-TOOLS are comparing it to the libraries listed below
Sorting:
- Fully Open Source FASOC generators built on top of open-source EDA tools☆276Updated last month
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆324Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆532Updated this week
- ☆321Updated 2 years ago
- Magic VLSI Layout Tool☆539Updated last month
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆284Updated 2 months ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆153Updated last month
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆378Updated this week
- Course material for a basic hands-on analog circuit design course with IC emphasis☆111Updated 2 weeks ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆418Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆324Updated 2 months ago
- SystemVerilog to Verilog conversion☆621Updated last month
- lowRISC Style Guides☆425Updated 8 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆178Updated 2 weeks ago
- 100 Days of RTL☆364Updated 8 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆209Updated 6 months ago
- Learning to do things with the Skywater 130nm process☆78Updated 4 years ago
- The UVM written in Python☆424Updated 3 weeks ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆397Updated 3 weeks ago
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆393Updated last year
- https://caravel-user-project.readthedocs.io☆198Updated 2 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆244Updated 9 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆318Updated this week
- Open Logic FPGA Standard Library☆586Updated last week
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆137Updated 2 months ago
- OpenSTA engine☆459Updated last week
- ☆296Updated 2 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆251Updated 2 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆150Updated 11 months ago
- A huge VHDL library for FPGA and digital ASIC development☆382Updated this week