Self-contained RTL to GDS flow for simple chip designs
☆73Jul 7, 2026Updated last month
Alternatives and similar repositories for microlane
Users that are interested in microlane are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆19Apr 20, 2026Updated 3 months ago
- A tiny FABulous FPGA for TTIHP26a☆15Apr 9, 2026Updated 4 months ago
- Project template for wafer.space MPW runs using the gf180mcu PDK☆42Updated this week
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 4 months ago
- A novel Design-for-Test flow using LibreLane☆45May 9, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆37Jul 23, 2026Updated 3 weeks ago
- Blender GDSII Importer with PDK Support☆139Jul 16, 2026Updated 3 weeks ago
- A configurable SRAM generator☆67Jun 28, 2026Updated last month
- A Risc-V SoC for Tiny Tapeout☆55Jul 12, 2026Updated last month
- Open Source Silicon Development Testing Unit using JTAG☆15Apr 25, 2026Updated 3 months ago
- Open-source PDK version manager☆58Jul 9, 2026Updated last month
- Digital Design Equivalence Checking☆97Updated this week
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- Cloneless1 is an open-source tamper-resistant cryptographic ASIC design☆24Jul 30, 2026Updated 2 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- HeiChips 2025 LibreLane Workshop☆16Aug 25, 2025Updated 11 months ago
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆19Updated this week
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 3 weeks ago
- Nix flake for more up-to-date versions of EDA tools☆33Updated this week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Updated this week
- ☆63Jul 11, 2025Updated last year
- wafer.space GF180MCU Run 1☆38Apr 27, 2026Updated 3 months ago
- 3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.☆23Jun 19, 2026Updated last month
- Logic circuit analysis and optimization☆52Feb 2, 2026Updated 6 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆22Dec 27, 2024Updated last year
- ASIC implementation flow infrastructure, successor to OpenLane☆508Updated this week
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 4 years ago
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated last year
- Agile Hardware Design Course☆15Nov 17, 2025Updated 8 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆19Jun 16, 2022Updated 4 years ago
- ☆65Mar 31, 2025Updated last year
- SystemVerilog design elaborator into word-level netlist form☆246Updated this week
- Parasitic Extraction for KLayout☆46Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 5 months ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Netlist API (and more) for EDA flow development☆159Updated this week
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 3 months ago
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year
- ☆23Updated this week
- JAX-based SPICE simulator with OpenVAF Verilog-A support☆23Jul 6, 2026Updated last month