Open-source PDK version manager
☆65Sep 19, 2026Updated this week
Alternatives and similar repositories for ciel
Users that are interested in ciel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆39Sep 10, 2026Updated last week
- Nix derivations for EDA tools☆12Nov 19, 2025Updated 10 months ago
- Custom IC Design Platform☆123Updated this week
- A novel Design-for-Test flow using LibreLane☆47May 9, 2026Updated 4 months ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆30Aug 24, 2026Updated 3 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆65Jul 11, 2025Updated last year
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 8 months ago
- An innovative Verilog-A compiler - reloaded☆50Aug 25, 2026Updated 3 weeks ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆110Aug 31, 2026Updated 3 weeks ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆45Aug 8, 2026Updated last month
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆24Updated this week
- Open source designs developed with the IHP 130nm BiCMOS Open PDK in the FMD_QNC project. Documentation at https://ihp-open-designlib.read…☆75Jun 5, 2026Updated 3 months ago
- Self-contained RTL to GDS flow for simple chip designs☆76Jul 7, 2026Updated 2 months ago
- ☆163Aug 19, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- ☆41Aug 28, 2026Updated 3 weeks ago
- Interchange formats for chip design.☆40Feb 15, 2026Updated 7 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).☆284Aug 21, 2026Updated last month
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆1,095Updated this week
- Nix flake for more up-to-date versions of EDA tools☆34Updated this week
- Fabric generator and CAD tools graphical frontend☆19Aug 5, 2025Updated last year
- Blender GDSII Importer with PDK Support☆140Sep 3, 2026Updated 2 weeks ago
- ASIC implementation flow infrastructure, successor to OpenLane☆550Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆67Sep 14, 2026Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆831Updated this week
- Development repository for openEMS workflow for IHP SG13G2☆69Updated this week
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆300Updated this week
- ☆67Mar 31, 2025Updated last year
- Cloneless1 is an open-source tamper-resistant cryptographic ASIC design☆27Jul 30, 2026Updated last month
- A python3 gm/ID starter kit☆99May 22, 2026Updated 4 months ago
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆26Aug 12, 2026Updated last month
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog file list pruner☆19Sep 14, 2026Updated last week
- Blocks & Bots: An Open Chip Playground augmented with LLMs. Please check: https://sscs.ieee.org/technical-committees/tc-ose/sscs-pico-des…☆86Updated this week
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆82Updated this week
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated last year
- Characterizer☆39Aug 26, 2026Updated 3 weeks ago
- Skywaters 130nm Klayout PDK☆37Jan 29, 2025Updated last year
- Parasitic capacitance analysis of foundry metal stackups☆21Jan 12, 2026Updated 8 months ago