raiyyanfaisal09 / Router1X3_RTL_DesignLinks
- A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a register module that can hold data packets momentarily, to pass onto three different FIFO memories along with a Finite State Machine and a Synchronizer that can manipulate the internal signals to carry out the ne…
☆10Updated 6 years ago
Alternatives and similar repositories for Router1X3_RTL_Design
Users that are interested in Router1X3_RTL_Design are comparing it to the libraries listed below
Sorting:
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- ☆20Updated 2 years ago
- Maven Silicon Project☆19Updated 6 years ago
- ☆17Updated 10 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆12Updated 2 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- System Verilog using Functional Verification☆12Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- Router 1 x 3 verilog implementation☆13Updated 3 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- A complete UVM TB for verification of single port 64KB RAM☆16Updated 4 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated 11 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- ☆16Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- ☆25Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- ☆12Updated 9 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 4 months ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago