raiyyanfaisal09 / Router1X3_RTL_Design
- A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a register module that can hold data packets momentarily, to pass onto three different FIFO memories along with a Finite State Machine and a Synchronizer that can manipulate the internal signals to carry out the ne…
☆10Updated 5 years ago
Alternatives and similar repositories for Router1X3_RTL_Design:
Users that are interested in Router1X3_RTL_Design are comparing it to the libraries listed below
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆12Updated 6 years ago
- Maven Silicon Project☆17Updated 6 years ago
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- Router 1 x 3 verilog implementation☆13Updated 3 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- System Verilog using Functional Verification☆10Updated 11 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- ☆19Updated 2 years ago
- ☆17Updated 9 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆12Updated 3 years ago
- ☆25Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- A complete UVM TB for verification of single port 64KB RAM☆15Updated 3 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆19Updated last month
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆12Updated 2 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆19Updated 8 months ago
- DDR3 function verification environment in UVM☆23Updated 7 years ago
- AXI Interconnect☆47Updated 3 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- ☆16Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- Verification IP for APB protocol☆60Updated 4 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- EE577b-Course-Project☆16Updated 4 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago