epfl-vlsc / parendi
Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
☆19Updated 11 months ago
Alternatives and similar repositories for parendi:
Users that are interested in parendi are comparing it to the libraries listed below
- ☆39Updated last month
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated last month
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆20Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆24Updated last year
- Fast Symbolic Repair of Hardware Design Code☆22Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- ☆13Updated 8 months ago
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 11 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 3 months ago
- A Rocket-based RISC-V superscalar in-order core☆30Updated this week
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- ☆18Updated this week
- Intel Compiler for SystemC☆23Updated last year
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 4 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆30Updated last week
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- Simple UVM environment for experimenting with Verilator.☆18Updated 2 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆29Updated 2 months ago