epfl-vlsc / parendi
Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
☆17Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for parendi
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 8 months ago
- ☆36Updated 6 months ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆13Updated 3 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆35Updated last year
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆11Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.☆12Updated 7 months ago
- ☆16Updated 4 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆34Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆55Updated last month
- A configurable SRAM generator☆40Updated this week
- DUTH RISC-V Superscalar Microprocessor☆28Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆92Updated 7 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago