epfl-vlsc / parendi
Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
☆19Updated 10 months ago
Alternatives and similar repositories for parendi:
Users that are interested in parendi are comparing it to the libraries listed below
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆20Updated 7 months ago
- Open source RTL simulation acceleration on commodity hardware☆23Updated last year
- ☆39Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated last month
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated 11 months ago
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- A Rocket-based RISC-V superscalar in-order core☆29Updated last week
- ☆17Updated 8 months ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆16Updated 3 months ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Lab assignments for the Agile Hardware Design course☆14Updated 10 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 10 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆57Updated 4 months ago
- ☆12Updated 7 months ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- CGRA framework with vectorization support.☆24Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- ☆15Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆25Updated last month
- ☆52Updated this week
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆27Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆59Updated 2 months ago