Alternatives and similar repositories for VeriSC:

Users that are interested in VeriSC are comparing it to the libraries listed below

• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• pulp-platform / pulp-ethernet
  ☆13Updated 3 weeks ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 2 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated 11 months ago
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆12Updated 11 months ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆16Updated this week
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 5 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 9 months ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated 11 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆22Updated 8 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆23Updated 2 months ago
• pulp-platform / axi_llc
  ☆25Updated last week
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆9Updated last year
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 2 months ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆34Updated 6 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 10 months ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year