OSCPU-Zhoushan / ZhoushanLinks
Open Source Chip Project by University (OSCPU) - Zhoushan Core
☆51Updated 3 years ago
Alternatives and similar repositories for Zhoushan
Users that are interested in Zhoushan are comparing it to the libraries listed below
Sorting:
- ☆86Updated 2 weeks ago
- ☆78Updated 4 months ago
- ☆67Updated 6 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆18Updated 2 years ago
- Advanced Architecture Labs with CVA6☆66Updated last year
- Modern co-simulation framework for RISC-V CPUs☆148Updated this week
- Pick your favorite language to verify your chip.☆64Updated this week
- ☆97Updated this week
- ☆66Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆178Updated 10 months ago
- ☆25Updated last month
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- XiangShan Frontend Develop Environment☆64Updated this week
- ☆64Updated 2 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆22Updated 2 years ago
- ☆42Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆38Updated this week
- Documentation for XiangShan Design☆30Updated last month
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆206Updated 2 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 4 months ago
- A Study of the SiFive Inclusive L2 Cache☆67Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Run rocket-chip on FPGA☆70Updated 9 months ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆77Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆36Updated 6 years ago
- ☆184Updated 2 months ago