Alternatives and similar repositories for Zhoushan

Users that are interested in Zhoushan are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆91Updated 3 months ago
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• OSCPU / yosys-sta
  ☆89Updated 2 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆76Updated this week
• OSCPU / chisel-playground
  ☆70Updated 11 months ago
• Jpz-sdju / trinity
  ☆32Updated 5 months ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• OpenXiangShan / GEM5
  ☆122Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆72Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆166Updated this week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆193Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated last week
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 9 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆77Updated 2 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆218Updated 2 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆46Updated 2 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆70Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆47Updated 3 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 4 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last month
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆224Updated 2 months ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆21Updated 7 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆135Updated 10 months ago