Alternatives and similar repositories for EECS-470-FinalProject

Users that are interested in EECS-470-FinalProject are comparing it to the libraries listed below

• mytbk / gem5-docs
  gem5 相关中文笔记
  ☆15Updated 3 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• jieltan / OpenCompArchCourse
  ☆22Updated 4 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• cry-daniel / Computer-Architecture-Learning
  ☆63Updated 2 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• miaochenlu / Gem5_tutorials
  ☆20Updated 2 months ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆22Updated 7 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• Jpz-sdju / trinity
  ☆24Updated last week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• OpenXiangShan / GEM5
  ☆93Updated this week
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆17Updated 3 months ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆28Updated 2 weeks ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆20Updated 7 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆31Updated 5 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆36Updated last month
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 2 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆17Updated 6 years ago
• kyaso / py-v
  A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.
  ☆16Updated last month
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 8 months ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆41Updated 2 years ago