Alternatives and similar repositories for EECS-470-FinalProject

Users that are interested in EECS-470-FinalProject are comparing it to the libraries listed below

• jieltan / OpenCompArchCourse
  ☆24Updated 4 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 3 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆70Updated 2 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 7 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• miaochenlu / Gem5_tutorials
  ☆22Updated 2 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆72Updated 2 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 4 years ago
• mytbk / gem5-docs
  gem5 相关中文笔记
  ☆17Updated 4 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆45Updated 2 years ago
• xinchen13 / gem5-noc
  NoC simulation using gem5 (a simple tul)
  ☆13Updated last year
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆28Updated last year
• arch-simulator-sig / simulator-paper
  ☆11Updated last year
• kiclu / rv6
  Pipelined 64-bit RISC-V core
  ☆15Updated last year
• OpenXiangShan / GEM5
  ☆122Updated this week
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆20Updated 9 months ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆21Updated 7 years ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆45Updated 2 years ago
• yousei-github / ChampSim-Ramulator
  A simulator integrates ChampSim and Ramulator.
  ☆19Updated 5 months ago
• Jpz-sdju / trinity
  ☆32Updated 5 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆31Updated 3 weeks ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆33Updated 11 months ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆47Updated 7 months ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆67Updated 8 months ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 4 years ago