LLM-Assisted Hardware Formal Verification Tool
☆111Jul 13, 2026Updated 2 weeks ago
Alternatives and similar repositories for rIC3
Users that are interested in rIC3 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Jul 4, 2025Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Reads a state transition system and performs property checking☆93Sep 12, 2025Updated 10 months ago
- A fork of Yosys that integrates the CellIFT pass☆14Apr 21, 2026Updated 3 months ago
- ☆33Nov 2, 2025Updated 8 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆16Aug 13, 2022Updated 3 years ago
- Pono: A flexible and extensible SMT-based model checker☆128Updated this week
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆69May 31, 2015Updated 11 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆112Updated this week
- ☆18Nov 19, 2023Updated 2 years ago
- A generic parser and tool package for the BTOR2 format.☆49Sep 18, 2025Updated 10 months ago
- ☆23Mar 12, 2026Updated 4 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 8 months ago
- ☆15Dec 6, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated 2 weeks ago
- work in progress, playing around with btor2 in rust☆15Updated this week
- ☆13Jan 20, 2023Updated 3 years ago
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 3 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated 2 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- SystemVerilog design elaborator into word-level netlist form☆243Updated this week
- AIGER And-Inverter-Graph Library☆105Feb 17, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- Research paper based on or related to ABC.☆72Jun 11, 2026Updated last month
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- ☆18Jul 12, 2024Updated 2 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆30Dec 23, 2025Updated 7 months ago
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays a…☆365Jul 21, 2026Updated last week
- Equivalence checking with Yosys☆59Updated this week
- ☆14Jan 3, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- design and verification of asynchronous circuits☆51Jul 9, 2026Updated 2 weeks ago
- All the tools you need to reproduce the CellIFT paper experiments☆24Feb 11, 2025Updated last year
- ☆15Jun 18, 2023Updated 3 years ago
- Recent papers related to hardware formal verification.☆78Sep 20, 2023Updated 2 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- Yosys RTLIL dialect for MLIR☆23Jun 12, 2025Updated last year