Example of how to use UVM with Verilator
☆50Apr 20, 2026Updated 6 months ago
Alternatives and similar repositories for verilator-uvm-example
Users that are interested in verilator-uvm-example are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilator open-source SystemVerilog simulator and lint system☆28Updated this week
- Test dashboard for verification features in Verilator☆35Updated this week
- SVA examples and demonstration☆18Sep 8, 2020Updated 6 years ago
- ☆143Aug 14, 2026Updated 2 months ago
- ☆11Dec 15, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This repo is created to include illustrative examples on object oriented design pattern in SV☆62Feb 25, 2023Updated 3 years ago
- RTLMeter benchmark suite☆34Oct 19, 2026Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆43Jun 24, 2026Updated 4 months ago
- CVA6 softcore contest☆24Jul 8, 2026Updated 3 months ago
- ☆30Oct 2, 2023Updated 3 years ago
- Coverview☆36Oct 5, 2026Updated 3 weeks ago
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆66Jul 25, 2026Updated 3 months ago
- Simple UVM environment for experimenting with Verilator.☆56Sep 9, 2026Updated last month
- The UVM written in Python☆572Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆149Oct 14, 2026Updated 2 weeks ago
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆105Mar 29, 2024Updated 2 years ago
- Python classes to create agnostic wave files for HDL simulator viewer☆15Oct 14, 2026Updated 2 weeks ago
- RISC-V Processor Implementation (RV32IM, TileLink-UL)☆26Apr 9, 2026Updated 6 months ago
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 7 years ago
- ☆15Dec 19, 2025Updated 10 months ago
- AMIQ Externally Controlled Test Bench☆12Jan 13, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- A Python package to use FPGA development tools programmatically.☆151Sep 21, 2026Updated last month
- Simulation VCD waveform viewer, using old Motif UI☆28Apr 8, 2023Updated 3 years ago
- ☆13Mar 30, 2020Updated 6 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆476Updated this week
- SystemVerilog linter☆394Nov 6, 2025Updated 11 months ago
- SystemVerilog design elaborator into word-level netlist form☆253Oct 20, 2026Updated last week
- Tools for manipulating Fast Signal Trace (FST) format waveforms.☆19Oct 11, 2026Updated 2 weeks ago
- Test suite designed to check compliance with the SystemVerilog standard.☆404Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Unified Coverage Interoperability Standard (UCIS)☆15Updated this week
- Python library for operations with VCD and other digital wave files☆55May 19, 2026Updated 5 months ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Aug 11, 2026Updated 2 months ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆33Aug 20, 2022Updated 4 years ago