☆35Mar 17, 2026Updated this week
Alternatives and similar repositories for sv-bugpoint
Users that are interested in sv-bugpoint are comparing it to the libraries listed below
Sorting:
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Mar 3, 2026Updated 2 weeks ago
- Coverview☆28Jan 29, 2026Updated last month
- work in progress, playing around with btor2 in rust☆12Feb 24, 2026Updated 3 weeks ago
- ☆14Jun 7, 2021Updated 4 years ago
- Connecting bv_decide to SMTLIB.☆13Jan 5, 2026Updated 2 months ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- ☆31Oct 2, 2023Updated 2 years ago
- ☆17Sep 9, 2024Updated last year
- Debug waveforms with GDB☆29Nov 12, 2025Updated 4 months ago
- Test dashboard for verification features in Verilator☆31Updated this week
- Extended and external tests for Verilator testing☆17Mar 11, 2026Updated last week
- SystemVerilog file list pruner☆17Mar 2, 2026Updated 2 weeks ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Raw image/video data analyzer☆48Jan 29, 2025Updated last year
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆20Apr 1, 2025Updated 11 months ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated last week
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Nov 11, 2025Updated 4 months ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆28Mar 31, 2025Updated 11 months ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Aug 30, 2023Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- ☆33Jan 7, 2025Updated last year
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆11Jul 4, 2025Updated 8 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆42Jul 17, 2024Updated last year
- rio-wayland shim server☆21Sep 10, 2023Updated 2 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆112Mar 13, 2026Updated last week
- ☆21Updated this week
- ☆35Feb 20, 2026Updated last month
- A SystemVerilog language server based on the Slang library.☆177Mar 9, 2026Updated last week
- Hardware Formal Verification Tool☆90Mar 14, 2026Updated last week
- SystemVerilog frontend for Yosys☆210Updated this week
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 4 months ago
- Filelist generator☆20Mar 3, 2026Updated 2 weeks ago
- Fast Symbolic Repair of Hardware Design Code☆33Jan 20, 2025Updated last year
- Egraphs Modulo Theories☆18Jun 10, 2025Updated 9 months ago
- Pythonic, Really Awesome V4L2 utility☆24Feb 16, 2024Updated 2 years ago
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated last month