antmicro / sv-bugpointLinks
☆34Updated 3 weeks ago
Alternatives and similar repositories for sv-bugpoint
Users that are interested in sv-bugpoint are comparing it to the libraries listed below
Sorting:
- A SystemVerilog language server based on the Slang library.☆104Updated this week
- SystemVerilog frontend for Yosys☆187Updated last week
- Hardware generator debugger☆77Updated last year
- Test dashboard for verification features in Verilator☆28Updated this week
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- A SystemVerilog source file pickler.☆60Updated last year
- SystemVerilog synthesis tool☆225Updated 10 months ago
- An automatic clock gating utility☆51Updated 9 months ago
- RISC-V Formal Verification Framework☆176Updated 2 weeks ago
- Determines the modules declared and instantiated in a SystemVerilog file☆49Updated last year
- ☆33Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆105Updated last week
- high-performance RTL simulator☆185Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆88Updated 3 months ago
- Mutation Cover with Yosys (MCY)☆90Updated last week
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆55Updated last year
- ☆113Updated 2 months ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 months ago
- Equivalence checking with Yosys☆54Updated last week
- A configurable SRAM generator☆57Updated 5 months ago
- design and verification of asynchronous circuits☆42Updated this week
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆58Updated 9 months ago
- 21st century electronic design automation tools, written in Rust.☆33Updated last week