AUCOHL / LighterView external linksLinks
An automatic clock gating utility
☆52Apr 15, 2025Updated 10 months ago
Alternatives and similar repositories for Lighter
Users that are interested in Lighter are comparing it to the libraries listed below
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Nov 10, 2025Updated 3 months ago
- ☆33Jan 7, 2025Updated last year
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- ASIC implementation flow infrastructure, successor to OpenLane☆290Updated this week
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- Description of Apple's LEAP ISA☆16Nov 21, 2022Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated this week
- Parasitic capacitance analysis of foundry metal stackups☆16Jan 12, 2026Updated last month
- ☆15Apr 30, 2021Updated 4 years ago
- SystemVerilog synthesis tool☆227Mar 10, 2025Updated 11 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated last month
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆22Jan 6, 2026Updated last month
- SystemVerilog frontend for Yosys☆198Feb 8, 2026Updated last week
- A complete open-source design-for-testing (DFT) Solution☆179Aug 30, 2025Updated 5 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆332Dec 2, 2025Updated 2 months ago
- Interchange formats for chip design.☆36Feb 3, 2026Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆80Jan 28, 2026Updated 2 weeks ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆106Feb 7, 2026Updated last week
- Integrated Circuit Layout☆57Feb 25, 2025Updated 11 months ago
- Hardware Description Library☆88Jan 29, 2026Updated 2 weeks ago
- Library of FPGA architectures☆30Jan 6, 2026Updated last month
- ☆99Updated this week
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- A 16-bit RISC-V Inspired ISA☆23Jul 19, 2025Updated 6 months ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆26Feb 2, 2026Updated last week
- Open-source PDK version manager☆39Nov 25, 2025Updated 2 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆167Dec 29, 2025Updated last month
- SystemVerilog file list pruner☆16Updated this week
- We open-source our layout level fast EM simulation tool, EMSim, to the public.☆14Feb 8, 2024Updated 2 years ago
- Logic circuit analysis and optimization☆45Feb 2, 2026Updated last week
- Elements Software Development Kit☆13Jan 8, 2026Updated last month
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆75Nov 19, 2025Updated 2 months ago
- SRAM Design using OpenSource Applications☆24Jul 16, 2021Updated 4 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆134Updated this week
- Fabric generator and CAD tools.☆217Feb 7, 2026Updated last week
- A configurable SRAM generator☆58Aug 19, 2025Updated 5 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83May 14, 2024Updated last year
- Hardware transactions library for Amaranth☆21Feb 6, 2026Updated last week