Alternatives and similar repositories for Lighter

Users that are interested in Lighter are comparing it to the libraries listed below

• pulp-platform / svase
  ☆32Updated 6 months ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 4 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated 3 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆146Updated last week
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆35Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 8 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆49Updated 5 years ago
• snishizawa / libretto
  Characterizer
  ☆29Updated 2 months ago
• efabless / caravel_user_project_analog
  ☆48Updated 5 months ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆42Updated 4 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• efabless / chipignite-resources
  ☆81Updated 2 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆21Updated 2 years ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆50Updated 5 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 2 months ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆48Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆41Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆152Updated 3 weeks ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆58Updated this week
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 8 months ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆71Updated 4 years ago