An automatic clock gating utility
☆53Apr 15, 2025Updated last year
Alternatives and similar repositories for Lighter
Users that are interested in Lighter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆175Nov 10, 2025Updated 9 months ago
- ☆16Apr 30, 2021Updated 5 years ago
- ☆33Jan 7, 2025Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 4 months ago
- A complete open-source design-for-testing (DFT) Solution☆203Aug 30, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISCV Core written in Calyx☆17Aug 16, 2024Updated 2 years ago
- SystemVerilog synthesis tool☆236Mar 10, 2025Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 5 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆29Dec 1, 2022Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 6 months ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- ☆127Updated this week
- ☆110Jun 20, 2025Updated last year
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆372Dec 2, 2025Updated 9 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Description of Apple's LEAP ISA☆17Nov 21, 2022Updated 3 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- Logic circuit analysis and optimization☆52Feb 2, 2026Updated 7 months ago
- A Python library for working with logic networks, synthesis, and optimization.☆88Updated this week
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆143Aug 23, 2026Updated 2 weeks ago
- A 16-bit RISC-V Inspired ISA☆33Jul 13, 2026Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆124Sep 20, 2023Updated 2 years ago
- ☆39Updated this week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- SystemVerilog file list pruner☆19Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆85May 14, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆793Aug 12, 2026Updated 3 weeks ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- Netlist API (and more) for EDA flow development☆160Updated this week
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Integrated Circuit Layout☆62Feb 25, 2025Updated last year
- ASIC implementation flow infrastructure, successor to OpenLane☆533Updated this week
- Hardware Description Library☆96Feb 17, 2026Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog design elaborator into word-level netlist form☆249Updated this week
- Parasitic capacitance analysis of foundry metal stackups☆21Jan 12, 2026Updated 7 months ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆81Nov 19, 2025Updated 9 months ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆20Mar 28, 2025Updated last year
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆16Jul 7, 2026Updated 2 months ago
- a curated "awesome list" of open-source hardware Intellectual Property (IP) blocks designed specifically for the SkyWater 130nm (SKY130) …☆30Apr 18, 2026Updated 4 months ago