AUCOHL / Lighter
An automatic clock gating utility
☆45Updated 8 months ago
Alternatives and similar repositories for Lighter:
Users that are interested in Lighter are comparing it to the libraries listed below
- ☆36Updated 2 years ago
- ☆31Updated 2 months ago
- Characterizer☆21Updated 7 months ago
- ☆33Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- SystemVerilog frontend for Yosys☆80Updated this week
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- ☆55Updated 2 years ago
- BAG framework☆40Updated 8 months ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- Prefix tree adder space exploration library☆57Updated 4 months ago
- ☆31Updated last year
- ☆33Updated 2 years ago
- ☆46Updated last month
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆26Updated 2 weeks ago
- RISC-V Nox core☆62Updated 7 months ago
- A SystemVerilog source file pickler.☆55Updated 5 months ago
- ☆33Updated 4 months ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- A configurable SRAM generator☆47Updated 2 months ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆25Updated 4 years ago
- A padring generator for ASICs☆25Updated last year
- AXI Formal Verification IP☆20Updated 3 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 4 months ago