dtcxzyw / static-keyLinks
Header-only C/C++ static keys to avoid the overhead of conditional branches
☆14Updated last year
Alternatives and similar repositories for static-key
Users that are interested in static-key are comparing it to the libraries listed below
Sorting:
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆21Updated last month
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆14Updated 4 months ago
- A 3d printed case design for Lichee Pi 4A☆12Updated 2 years ago
- Relaxed Rust (for cats)☆16Updated 5 years ago
- An implementation of memcpy for amd64 with clang/gcc☆15Updated 3 years ago
- compile-time DFA-based regular expression engine with C++ template and constexpr☆55Updated 5 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- CIDR union / subtraction☆14Updated this week
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- RV32I by cats☆16Updated last year
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- An April fools joke, a llvm backend to CMake☆49Updated 3 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Updated 5 years ago
- My knowledge base☆63Updated this week
- Yet another raytracer☆8Updated 2 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆25Updated last month
- A Rust style C++ library.☆19Updated 2 years ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- Apple Silicon TSO Enabler for Linux☆17Updated last year
- What if everything is a io_uring?☆16Updated 2 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 5 years ago
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Binary translation in Rust☆13Updated 5 years ago
- Microarchitecture diagrams of several CPUs☆37Updated 3 weeks ago
- A naive key-value database as the project of Storage Technology Foundations course☆10Updated 6 years ago