mikeurbach / egg-netlist-synthesizer
Using e-graphs to synthesize netlists from boolean logic.
☆14Updated last year
Alternatives and similar repositories for egg-netlist-synthesizer:
Users that are interested in egg-netlist-synthesizer are comparing it to the libraries listed below
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆18Updated this week
- A Hardware Pipeline Description Language☆44Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆26Updated 6 months ago
- BTOR2 MLIR project☆20Updated last year
- CoreIR Symbolic Analyzer☆63Updated 4 years ago
- Verilog AST☆21Updated last year
- ☆12Updated 3 years ago
- ☆16Updated 6 months ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Updated last year
- 21st century electronic design automation tools, written in Rust.☆16Updated this week
- Fast PnR toolchain for CGRA☆18Updated 5 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆26Updated 2 months ago
- ☆40Updated 3 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- Fast Symbolic Repair of Hardware Design Code☆20Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- ☆23Updated 3 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆13Updated 2 years ago
- DASS HLS Compiler☆27Updated last year
- A hardware synthesis framework with multi-level paradigm☆36Updated last week
- Equivalence checking with Yosys☆38Updated last month
- The source code to the Voss II Hardware Verification Suite☆53Updated 4 months ago
- an experiment to run plugin in firtool pipeline☆9Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Hardware Model Checker☆26Updated this week
- ☆10Updated last year