Alternatives and similar repositories for egg-netlist-synthesizer:

Users that are interested in egg-netlist-synthesizer are comparing it to the libraries listed below

• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆29Updated this week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆20Updated 3 months ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 2 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆43Updated last year
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆28Updated 9 months ago
• iscas-tis / CHA
  ☆18Updated 9 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆42Updated last week
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆35Updated 5 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 weeks ago
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆13Updated 4 months ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated 8 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆70Updated 4 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆13Updated 2 years ago
• euphoric-hardware / simcommand
  SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
  ☆14Updated last year
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆27Updated 3 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆9Updated 5 months ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆12Updated 3 weeks ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆44Updated last week
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• uenoku / firtool-standalone-plugin
  an experiment to run plugin in firtool pipeline
  ☆9Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated 2 months ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated 3 weeks ago