Alternatives and similar repositories for egg-netlist-synthesizer

Users that are interested in egg-netlist-synthesizer are comparing it to the libraries listed below

• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated last week
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆33Updated 4 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• iscas-tis / CHA
  ☆19Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆34Updated 11 months ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆53Updated 2 weeks ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated this week
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated 4 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated last month
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 7 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• vegaluisjose / reticle
  ☆40Updated 4 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• euphoric-hardware / simcommand
  SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
  ☆14Updated 2 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last month
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 4 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago