peilin-chen / Zhulong-RISCV-CPU
CPU Design Based on RISCV ISA
☆95Updated 9 months ago
Alternatives and similar repositories for Zhulong-RISCV-CPU:
Users that are interested in Zhulong-RISCV-CPU are comparing it to the libraries listed below
- AXI协议规范中文翻译版☆141Updated 2 years ago
- AXI总线连接器☆96Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆39Updated 7 months ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆67Updated this week
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆82Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆137Updated last month
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆13Updated 10 months ago
- 数字IC秋招项目、手撕代码☆34Updated 11 months ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆153Updated 4 months ago
- ☆128Updated 3 weeks ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- ☆79Updated last month
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- commit rtl and build cosim env☆36Updated 11 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆194Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆33Updated 2 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆166Updated 6 years ago
- ☆63Updated 2 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- ☆41Updated 2 years ago
- ☆59Updated 9 years ago
- ☆141Updated last month
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- Some useful documents of Synopsys☆67Updated 3 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- IC implementation of Systolic Array for TPU☆204Updated 5 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago