CPU Design Based on RISCV ISA
☆135Jun 14, 2024Updated last year
Alternatives and similar repositories for Zhulong-RISCV-CPU
Users that are interested in Zhulong-RISCV-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- 5 stage pipeline, single cycle risc-V implementation☆30Mar 9, 2024Updated 2 years ago
- verilog☆21Jun 26, 2023Updated 2 years ago
- riscv指令集，单周期以及五级流水线CPU☆119Jan 6, 2025Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- ☆12Sep 18, 2024Updated last year
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- FPGA Innovation Design Competition：RISC-V Processor-based Hardware and Software Design in PGL22G☆12Sep 1, 2023Updated 2 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 6 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆28Apr 7, 2025Updated 11 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆77Jan 15, 2023Updated 3 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆233Oct 16, 2025Updated 5 months ago
- ☆38Aug 12, 2015Updated 10 years ago
- 基4booth乘法器设计与验证☆15Apr 28, 2024Updated last year
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆14Nov 12, 2025Updated 4 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- ☆73Apr 23, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,787Aug 6, 2025Updated 7 months ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 5 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆128Aug 27, 2024Updated last year
- A MATLAB code package to perform Weighted Sparse Bayesian Learning for EIT using Bound-Optimization. Allows parametrization, compares qua…☆17Jun 18, 2023Updated 2 years ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆35Updated this week
- NUDT 高级体系结构实验☆35Sep 21, 2024Updated last year
- ☆75Jan 19, 2016Updated 10 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- ☆20Jun 23, 2024Updated last year
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- 哈工大2023处理器设计与计算机体系结构实验☆28Sep 3, 2024Updated last year
- A very simple and easy to understand RISC-V core.☆1,428Nov 9, 2023Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆58Nov 22, 2023Updated 2 years ago