Alternatives and similar repositories for Zhulong-RISCV-CPU:

Users that are interested in Zhulong-RISCV-CPU are comparing it to the libraries listed below

• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆138Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆12Updated 9 months ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆36Updated 6 months ago
• OSCPU / ysyxSoC
  ☆79Updated last week
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆34Updated 9 months ago
• RV-BOSC / OpenNoC
  ☆114Updated last week
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆25Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆94Updated 4 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆137Updated 3 months ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆52Updated this week
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆77Updated 3 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆77Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆131Updated 2 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆62Updated 6 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆145Updated last year
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆31Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆106Updated 10 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• ForrestBlue / cortexm0ds
  ☆57Updated 9 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆189Updated 3 months ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆128Updated 3 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆121Updated 2 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆18Updated last year
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆44Updated 3 years ago
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆32Updated last week
• XueTianyu24 / cnn_accelerator
  【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
  ☆135Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆186Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆88Updated 4 years ago