peilin-chen / Zhulong-RISCV-CPU
CPU Design Based on RISCV ISA
☆78Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for Zhulong-RISCV-CPU
- AXI协议规范中文翻译版☆132Updated 2 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆31Updated 3 months ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆122Updated 3 weeks ago
- AXI总线连接器☆91Updated 4 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆11Updated 6 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆69Updated 2 years ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- Step by step tutorial for building CortexM0 SoC☆36Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated this week
- ☆76Updated 2 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- CNN accelerator implemented with Spinal HDL☆136Updated 9 months ago
- 数字IC秋招项目、手撕代码☆33Updated 7 months ago
- Collect some IC textbooks for learning.☆104Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆25Updated 2 years ago
- ☆36Updated 2 years ago
- ☆62Updated 3 months ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆27Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆168Updated last year
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆24Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- ☆93Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆35Updated 3 years ago
- ☆52Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆54Updated 3 months ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆67Updated 2 years ago
- IC implementation of Systolic Array for TPU☆155Updated last month