Alternatives and similar repositories for Zhulong-RISCV-CPU:

Users that are interested in Zhulong-RISCV-CPU are comparing it to the libraries listed below

• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆137Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆93Updated 4 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆12Updated 8 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆38Updated 4 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆132Updated 2 months ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆35Updated 5 months ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆75Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆103Updated 10 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆130Updated last month
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆29Updated 2 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆37Updated 2 years ago
• OSCPU / ysyxSoC
  ☆78Updated 3 weeks ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆61Updated 6 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆72Updated 3 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆48Updated 3 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆33Updated 8 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆25Updated 2 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆36Updated 5 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆42Updated 3 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆85Updated 4 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆39Updated 2 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆174Updated last year
• Advanced-Microelectronics-Group / OpenC910_Modified
  commit rtl and build cosim env
  ☆36Updated 9 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆144Updated 11 months ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆193Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆118Updated 2 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆36Updated 2 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆52Updated 8 years ago
• RongyeL / easy_axi
  Learn the basics of AXI against the code and protocol
  ☆11Updated 2 years ago