Alternatives and similar repositories for booth-multiplier:

Users that are interested in booth-multiplier are comparing it to the libraries listed below

• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆42Updated 7 months ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆92Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆41Updated 4 years ago
• OSCPU / ysyxSoC
  ☆82Updated last month
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• dldldlfma / super_small_toy_tpu
  ☆33Updated 4 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆44Updated 5 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆100Updated 9 months ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆16Updated 11 months ago
• ChunxuGuo / SummerSchool2022
  ☆61Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆98Updated 4 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆62Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆147Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆59Updated last month
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆41Updated last month
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆18Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 3 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆142Updated 2 years ago
• Swingfal1 / booth_multiplier_radix_4
  Verilog program
  ☆13Updated 4 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆104Updated 4 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆160Updated 5 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆23Updated 2 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆29Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• OSCPU / yosys-sta
  ☆61Updated 3 months ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆52Updated 3 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆19Updated last year