Alternatives and similar repositories for booth-multiplier

Users that are interested in booth-multiplier are comparing it to the libraries listed below

• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆55Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆130Updated 3 months ago
• dldldlfma / super_small_toy_tpu
  ☆43Updated 4 years ago
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆61Updated 5 months ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆100Updated last month
• 19801201 / Ultra_low_power_CNN_Accelerated
  ☆10Updated 3 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆273Updated 10 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆115Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆164Updated 5 years ago
• BIGWJZ / VLSI-DSP-Review
  ☆72Updated 5 years ago
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆42Updated 2 years ago
• WeitaoZhu / CMOS_VLSI_Design
  COMS 超大规模集成电路设计书籍
  ☆27Updated 3 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆46Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆222Updated 2 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆121Updated last year
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆20Updated last year
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆186Updated last year
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆86Updated 7 months ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆152Updated last year
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆192Updated 7 years ago
• YutongChenVictor / Fpga-accelerator-demos
  some interesting demos for starters
  ☆83Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated this week
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 4 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆195Updated 10 months ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆162Updated 3 years ago
• gl9544 / vit_transformer_fpga
  ☆14Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆187Updated 2 months ago