luzhixing12345 / archlabView external linksLinks
NUDT 高级体系结构实验
☆35Sep 21, 2024Updated last year
Alternatives and similar repositories for archlab
Users that are interested in archlab are comparing it to the libraries listed below
Sorting:
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 8 months ago
- An exquisite superscalar RV32GC processor.☆165Jan 13, 2025Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated last year
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated last year
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Feb 4, 2026Updated last week
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆15Sep 27, 2022Updated 3 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- ☆18Aug 1, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- Simple UVM environment for experimenting with Verilator.☆28Nov 3, 2025Updated 3 months ago
- ☆90Nov 12, 2025Updated 3 months ago
- ☆22Nov 3, 2025Updated 3 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- ordspecsim: The Swarm architecture simulator☆24Feb 15, 2023Updated 2 years ago
- Build an open source, extremely simple DMA.☆23Feb 17, 2019Updated 6 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆36Oct 21, 2021Updated 4 years ago
- The MiniDecaf test cases.☆18May 15, 2025Updated 8 months ago
- ☆26Mar 19, 2021Updated 4 years ago
- A cache simulator designed to be used with memory access traces obtained from Pin (www.pintool.org)☆23Aug 21, 2018Updated 7 years ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- ☆12Aug 12, 2022Updated 3 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Feb 20, 2024Updated last year
- riscv指令集,单周期以及五级流水线CPU☆107Jan 6, 2025Updated last year
- 南大2024操作系统课程实验☆28Mar 9, 2025Updated 11 months ago
- 快速陷入处理☆39Jan 22, 2026Updated 3 weeks ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- A reference book on System-on-Chip Design☆40Jun 16, 2025Updated 7 months ago
- 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设,支持运行主线Linux。A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals ar…☆92Oct 1, 2024Updated last year
- Design and optimize variational quantum sensors☆11Dec 10, 2024Updated last year
- This repository contains getting started projects related to all PSoC4 pioneer kits.☆13Oct 30, 2018Updated 7 years ago
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Oct 27, 2018Updated 7 years ago
- 经典的嵌 入式OS - ucos-II 2.52版本全注释,仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- ☆12May 26, 2025Updated 8 months ago
- Inverse Quantum-Optical Design of High-Dimensional Qudits☆17Aug 2, 2022Updated 3 years ago
- Collection of popular, highly recommended, highly influential CS books☆11Jul 4, 2022Updated 3 years ago
- ☆42Oct 7, 2023Updated 2 years ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago