A Verilog implementation of a processor cache.
☆37Dec 29, 2017Updated 8 years ago
Alternatives and similar repositories for Processor-Cache
Users that are interested in Processor-Cache are comparing it to the libraries listed below
Sorting:
- Simple cache design implementation in verilog☆55Nov 20, 2023Updated 2 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- Two Level Cache Controller implementation in Verilog HDL☆60Jul 9, 2020Updated 5 years ago
- ☆14Feb 24, 2025Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- Various caches written in Verilog-HDL☆128Apr 24, 2015Updated 10 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 4 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆12Aug 21, 2023Updated 2 years ago
- A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memo…☆22May 24, 2017Updated 8 years ago
- SPI core☆12Jul 17, 2014Updated 11 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- ☆10Jun 9, 2022Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆68Jul 25, 2023Updated 2 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- ☆55Jun 19, 2021Updated 4 years ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 13 years ago
- Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog☆20Mar 11, 2021Updated 5 years ago
- CPU Design Based on RISCV ISA☆133Jun 14, 2024Updated last year
- Zucker SOC☆15Jun 11, 2025Updated 9 months ago
- ☆18Jun 3, 2019Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- ☆17Feb 9, 2023Updated 3 years ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago