Alternatives and similar repositories for Processor-Cache

Users that are interested in Processor-Cache are comparing it to the libraries listed below

• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆53Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆42Updated 3 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆45Updated 2 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆24Updated 7 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆32Updated last year
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆54Updated 4 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• psnjk / SimpleCache
  Simple cache design implementation in verilog
  ☆55Updated 2 years ago
• pulp-platform / axi_llc
  ☆32Updated 3 weeks ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆37Updated 9 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆34Updated 7 months ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 7 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆24Updated 3 months ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆31Updated 10 months ago
• pulp-platform / apb
  APB Logic
  ☆22Updated last month
• kuladeepsaireddy / OpenNoc
  ☆39Updated 6 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆16Updated 5 years ago
• mbits-mirafra / axi4_avip
  ☆38Updated 6 months ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆66Updated 3 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆12Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago