woshiyyya / RISCV-CPULinks
Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
☆20Updated 6 years ago
Alternatives and similar repositories for RISCV-CPU
Users that are interested in RISCV-CPU are comparing it to the libraries listed below
Sorting:
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- ☆37Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- ☆31Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- ☆56Updated 6 years ago
- Advanced Architecture Labs with CVA6☆70Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- ☆65Updated 3 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆36Updated last year
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- ☆31Updated 3 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆78Updated 11 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆138Updated 5 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆15Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆69Updated 5 years ago