Alternatives and similar repositories for RISCV-CPU

Users that are interested in RISCV-CPU are comparing it to the libraries listed below

• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated last year
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆54Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• OSCPU / ysyxSoC
  ☆86Updated 2 weeks ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆51Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆59Updated last year
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Jpz-sdju / trinity
  ☆20Updated last month
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆12Updated 2 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• jm2000 / RISCV-FPU
  Basic floating-point components for RISC-V processors
  ☆10Updated 7 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• pulp-platform / fpu
  ☆48Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆54Updated 9 months ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆148Updated this week
• ytliu74 / RISCV_Verilog
  RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.
  ☆18Updated last year
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆25Updated last year
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆75Updated 10 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆40Updated 3 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆43Updated last year