woshiyyya / RISCV-CPULinks
Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
☆18Updated 6 years ago
Alternatives and similar repositories for RISCV-CPU
Users that are interested in RISCV-CPU are comparing it to the libraries listed below
Sorting:
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆161Updated last month
- ☆34Updated 6 years ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago
- ☆29Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- ☆43Updated 3 years ago
- ☆76Updated 10 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- ☆86Updated 2 months ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- ☆51Updated 6 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated this week
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…☆9Updated 5 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆8Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆49Updated 5 years ago
- Digital system design: Training lessons and exercise projects for students☆10Updated 2 years ago
- ☆67Updated 9 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆103Updated 4 months ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- CPU Design Based on RISCV ISA☆117Updated last year