Alternatives and similar repositories for RISC_V_RV32I_5stage_pipeline

Users that are interested in RISC_V_RV32I_5stage_pipeline are comparing it to the libraries listed below

• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆126Updated last year
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆101Updated 11 months ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆120Updated 2 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆32Updated 3 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆166Updated 3 years ago
• RongyeL / EasyAXI
  ☆82Updated 3 weeks ago
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆391Updated 2 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆64Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆113Updated 3 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆153Updated 2 weeks ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆106Updated 4 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆156Updated 6 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆74Updated 8 months ago
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆62Updated 2 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆72Updated 2 years ago
• leesum1 / ysyx
  一生一芯项目
  ☆17Updated 2 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆153Updated 6 years ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆368Updated 2 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆210Updated 2 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆279Updated 2 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆54Updated last year
• ForrestBlue / cortexm0ds
  ☆73Updated 9 years ago
• xupsh / Digital-Design-Lab
  ☆227Updated 4 years ago
• flytt-away / FPGA-Video-Capture
  2023集创赛紫光同创杯一等奖项目
  ☆141Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆234Updated last year
• LinHuangnan / RiscV_GameConsole_FPGA
  FPGA创新设计大赛全国二等奖，Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)
  ☆11Updated last year
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆159Updated 3 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆75Updated 4 years ago