Alternatives and similar repositories for RISC_V_RV32I_5stage_pipeline:

Users that are interested in RISC_V_RV32I_5stage_pipeline are comparing it to the libraries listed below

• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆138Updated 2 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆88Updated 8 months ago
• OSCPU / ysyxSoC
  ☆79Updated this week
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆101Updated 2 years ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆113Updated 2 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆36Updated 6 months ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆18Updated last year
• OpenXiangShan / XS-Verilog-Library
  ☆38Updated 2 years ago
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆46Updated last year
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆139Updated 2 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• OSCPU / ysyx-exam
  ☆20Updated last year
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆106Updated 12 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆94Updated 4 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆25Updated 2 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆195Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆121Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆348Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆131Updated 5 months ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆58Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆114Updated this week
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆72Updated 3 years ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆52Updated this week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆131Updated 2 months ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆95Updated 5 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆135Updated 3 months ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆52Updated 8 years ago