Alternatives and similar repositories for FPGA_Competition-RISC-V_Processor-in-PGL22G

Users that are interested in FPGA_Competition-RISC-V_Processor-in-PGL22G are comparing it to the libraries listed below

• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆40Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆67Updated 2 years ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆28Updated 5 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆16Updated 5 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• OSCPU / yosys-sta
  ☆64Updated last month
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆65Updated 3 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆16Updated 6 years ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 9 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated last year
• Reconfigurable-Computing / Vitis_workflow
  Vitis 部署加速器工作流介绍
  ☆10Updated 4 months ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆11Updated 4 months ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆17Updated 5 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆40Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• RealJustinNi / EE219-AICS-2024
  ☆13Updated 4 months ago
• ZLkanyo009 / Yolo-compression-and-deployment-in-FPGA
  基于FPGA量化的人脸口罩检测
  ☆23Updated 3 years ago
• ChunxuGuo / SummerSchool2022
  ☆61Updated 2 years ago
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆20Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• OSCPU / ysyx-exam
  ☆21Updated last year