Alternatives and similar repositories for FPGA_Competition-RISC-V_Processor-in-PGL22G

Users that are interested in FPGA_Competition-RISC-V_Processor-in-PGL22G are comparing it to the libraries listed below

• Yawei-Ding / ysyx_riscv64_cpu
  ☆64Updated 2 years ago
• OSCPU / yosys-sta
  ☆64Updated 3 weeks ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆27Updated 4 years ago
• OSCPU / ysyxSoC
  ☆86Updated 2 weeks ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆40Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆36Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 11 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆43Updated 4 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆20Updated 2 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆15Updated 5 years ago
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• Reconfigurable-Computing / Vitis_workflow
  Vitis 部署加速器工作流介绍
  ☆10Updated 4 months ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆22Updated last year
• ganyunhan / IC-Design-Contest-ARM-CUP
  集成电路设计大赛ARM杯作品，获得2021年ARM企业杯
  ☆14Updated 3 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆11Updated 3 months ago
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆22Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• BriMonzZY / multi-mode-fft-processor
  R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
  ☆11Updated last week
• ChunxuGuo / SummerSchool2022
  ☆61Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆100Updated 2 months ago
• tastynoob / FPGA_network
  ☆37Updated 3 years ago
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆46Updated last year
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆26Updated 3 months ago