xiaowuzxc / SparrowRV
An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
☆62Updated 2 years ago
Alternatives and similar repositories for SparrowRV:
Users that are interested in SparrowRV are comparing it to the libraries listed below
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆68Updated 3 years ago
- ☆64Updated 2 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- OpenXuantie - OpenE902 Core☆143Updated 9 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆115Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆58Updated 3 years ago
- upgrade to e203 (a risc-v core)☆41Updated 4 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆154Updated last year
- AXI协议规范中文翻译版☆145Updated 2 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆63Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 10 months ago
- ☆85Updated 2 months ago
- OpenXuantie - OpenE906 Core☆138Updated 9 months ago
- Cortex M0 based SoC☆72Updated 3 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆125Updated 5 years ago
- CPU Design Based on RISCV ISA☆105Updated 10 months ago
- ☆63Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- Nuclei Board Labs☆58Updated last year
- ☆36Updated 6 years ago
- ☆62Updated 3 months ago
- ☆63Updated 4 years ago
- Step by step tutorial for building CortexM0 SoC☆37Updated 3 years ago
- SDRAM controller with AXI4 interface☆90Updated 5 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆187Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆143Updated last week
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆52Updated 9 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆27Updated 2 years ago