xiaowuzxc / SparrowRVView external linksLinks
An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
☆75Jan 15, 2023Updated 3 years ago
Alternatives and similar repositories for SparrowRV
Users that are interested in SparrowRV are comparing it to the libraries listed below
Sorting:
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Oct 3, 2023Updated 2 years ago
- Code examples for Sipeed Tang Nano 9K FPGA board including HDMI 720p and PSRAM controller usage.☆19Aug 21, 2022Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- ☆10Jan 30, 2017Updated 9 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated 11 months ago
- Verilog modules for software-defined radio.☆18Dec 31, 2012Updated 13 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆78Jun 10, 2021Updated 4 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- ☆10Apr 4, 2025Updated 10 months ago
- A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread.☆12Jan 18, 2021Updated 5 years ago
- 基于Risc-V的计算机体系结构设计。一栈式打通riscv架构硬件模拟器、操作系统、应用层！☆18Nov 25, 2024Updated last year
- ☆12Jul 20, 2022Updated 3 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- AXI4-Stream FIR filter IP☆19Nov 4, 2022Updated 3 years ago
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated last month
- Simple MOD player library written in C☆19Jan 30, 2026Updated 2 weeks ago
- Raspberry Pi Pico (RP2040) playground☆19Nov 11, 2024Updated last year
- ☆21Dec 9, 2018Updated 7 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- TangPrimer-20K-example project☆225Oct 17, 2024Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- Experiments with Marsohod3GW board with Gowin FPGA chip☆17May 8, 2025Updated 9 months ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- S/PDIF recorder to WAV on microSD card for Raspberry Pi Pico series☆21Jan 28, 2026Updated 2 weeks ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆43Apr 11, 2024Updated last year
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆16May 23, 2019Updated 6 years ago
- USB serial device (CDC-ACM)☆44Jun 28, 2020Updated 5 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- The Ultra-Low Power RISC-V Core☆1,733Aug 6, 2025Updated 6 months ago
- Benchmarks set written in C#, Java, PHP, JS, Python, Lua, Go☆23Sep 30, 2025Updated 4 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Dec 3, 2020Updated 5 years ago
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33May 17, 2020Updated 5 years ago
- SERV RISC-V sample for Tang Nano FPGA board☆19Dec 17, 2019Updated 6 years ago
- Build an open source, extremely simple DMA.☆23Feb 17, 2019Updated 6 years ago
- Release KiteRF is a SDR system with K210 & FPGA & ESP32 as its core controller, which make SDR more intelligent, portable and cheap.☆25May 6, 2020Updated 5 years ago
- forked from https://github.com/riscv/riscv-openocd.git,and add falsh support for LicheeTang☆24Oct 18, 2021Updated 4 years ago
- ☆107Mar 1, 2023Updated 2 years ago