xiaowuzxc / SparrowRV
An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
☆54Updated last year
Related projects ⓘ
Alternatives and complementary repositories for SparrowRV
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆20Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆67Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- ☆63Updated 2 years ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆99Updated 2 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆143Updated 11 months ago
- OpenXuantie - OpenE902 Core☆137Updated 4 months ago
- ☆36Updated 2 years ago
- ☆43Updated 4 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 2 years ago
- ☆76Updated 2 months ago
- Cortex M0 based SoC☆70Updated 3 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆62Updated 2 years ago
- AXI协议规范中 文翻译版☆132Updated 2 years ago
- CPU Design Based on RISCV ISA☆76Updated 5 months ago
- ☆61Updated 3 weeks ago
- SpinalHDL-tutorial based on Jupyter Notebook☆129Updated 5 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆123Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆199Updated 4 years ago
- OpenXuantie - OpenE906 Core☆137Updated 4 months ago
- Nuclei Board Labs☆52Updated 10 months ago
- The Ultra-Low Power RISC Core☆15Updated 4 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆36Updated last year
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆31Updated 3 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆46Updated 2 years ago
- ☆62Updated 3 months ago
- ☆16Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago