An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
☆78Jan 15, 2023Updated 3 years ago
Alternatives and similar repositories for SparrowRV
Users that are interested in SparrowRV are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆30Oct 3, 2023Updated 2 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆24Jul 12, 2023Updated 2 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆79Jun 10, 2021Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆170May 10, 2025Updated last year
- CPU Design Based on RISCV ISA☆139Jun 14, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆16May 23, 2019Updated 7 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- things about Verilog hardware description language☆19Sep 18, 2018Updated 7 years ago
- ☆10Apr 4, 2025Updated last year
- 基于Risc-V的计算机体系结构设计。一栈式打通riscv架构硬件模拟器、操作系统、应用层!☆21Nov 25, 2024Updated last year
- A very simple and easy to understand RISC-V core.☆1,472Nov 9, 2023Updated 2 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Dec 3, 2020Updated 5 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- FPGA based, Real-time processing of audio, including voiceprint recognition, adaptive noise suppression, et al.☆16May 8, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Jul 20, 2022Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,840Aug 6, 2025Updated 9 months ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 6 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆32Mar 7, 2024Updated 2 years ago
- FPGA Innovation Design Competition:RISC-V Processor-based Hardware and Software Design in PGL22G☆12Sep 1, 2023Updated 2 years ago
- Code examples for Sipeed Tang Nano 9K FPGA board including HDMI 720p and PSRAM controller usage.☆22Aug 21, 2022Updated 3 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- 基于w5500官方库ioLibrary_Driver,在STM32F103RC上实现了mqtt的功能☆12Jul 11, 2018Updated 7 years ago
- ☆31Jun 8, 2022Updated 3 years ago
- RISC-V Summit China 2023☆40Sep 27, 2023Updated 2 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- ☆10Jan 30, 2017Updated 9 years ago
- C-library for LCD display 16x2☆12Jan 8, 2026Updated 4 months ago
- Yet another free 8051 FPGA core☆38Sep 16, 2018Updated 7 years ago
- FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope☆14Sep 5, 2025Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…☆81Apr 15, 2025Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆130Aug 29, 2022Updated 3 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆199Oct 9, 2019Updated 6 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,843Mar 24, 2021Updated 5 years ago