Azalea8 / riscv_cpuLinks
riscv指令集,单周期以及五级流水线CPU
☆79Updated 6 months ago
Alternatives and similar repositories for riscv_cpu
Users that are interested in riscv_cpu are comparing it to the libraries listed below
Sorting:
- CPU Design Based on RISCV ISA☆118Updated last year
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆29Updated 3 years ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆61Updated last year
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆106Updated last week
- 5 stage pipeline, single cycle risc-V implementation☆22Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆84Updated 5 years ago
- This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…☆68Updated 3 months ago
- ☆68Updated 2 years ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆28Updated 6 months ago
- AXI协议规范中文翻译版☆159Updated 3 years ago
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆15Updated 11 months ago
- 数字IC设计 学习笔记☆151Updated 3 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 2 months ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆148Updated 6 years ago
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆14Updated 3 years ago
- ☆156Updated this week
- Uart transport + image processing + VGA display 基于FPGA的图像处理,包括Uart和VGA☆14Updated 5 years ago
- ☆86Updated 3 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆176Updated 9 months ago
- ☆82Updated 2 weeks ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆139Updated last year
- 复旦大学 数字逻辑与部件设计实验 2020秋☆51Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆52Updated 11 months ago
- NJU Virtual Board☆285Updated 3 weeks ago
- ☆66Updated last year
- 中国科学技术大学龙芯杯参赛作品仓库合集☆16Updated 10 months ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆93Updated 3 years ago
- 一生一芯项目☆13Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆25Updated last year